Data Sheet No. PD94144
IRU3018
5-BIT PROGRAMMABLE SYNCHRONOUS BUCK CONTROLLER IC,
LDO CONTROLLER AND 200mA ON-BOARD LDO REGULATOR
FEATURES
DESCRIPTION
Provides single chip solution for Vcore, GTL+ & clock
supply
200mA On-Board LDO Regulator
Designed to meet the latest Intel specification for
Pentium II™
On-Board DAC programs the output voltage from
1.3V to 3.5V
Linear regulator controller on board for 1.5V GTL+
supply
Loss-less Short Circuit Protection with HICCUP
Synchronous operation allows maximum efficiency
patented architecture allows fixed frequency opera-
tion as well as 100% duty cycle during dynamic
load
Soft-Start
High current totem pole driver for direct driving of the
external power MOSFET
Power Good Function monitors all outputs
Over-Voltage Protection circuitry protects the
switcher output and generates a fault signal
Thermal Shutdown
Logic Level Enable Input
The IRU3018 controller IC is specifically designed to meet
Intel specification for Pentium II™ microprocessor appli-
cations as well as the next generation of P6 family pro-
cessors. The IRU3018 provides a single chip controller
IC for the Vcore, LDO controller for GTL+ and an internal
200mA regulator for clock supply which are required for
the Pentium II applications. These devices feature a pat-
ented topology that in combination with a few external
components as shown in the typical application circuit,
will provide in excess of 18A of output current for an on-
board DC-DC converter while automatically providing the
right output voltage via the 5-bit internal DAC. The
IRU3018 also features loss-less current sensing for both
switchers by using the R
DS(ON)
of the high-side power
MOSFET as the sensing resistor, internal current limit-
ing for the clock supply, and a Power Good window com-
parator that switches its open collector output low when
any one of the outputs is outside of a pre-programmed
window. Other features of the device are: Under-voltage
lockout for both 5V and 12V supplies, an external pro-
grammable soft-start function, programming the oscilla-
tor frequency via an external resistor, Over-Voltage Pro-
tection (OVP) circuitry for both switcher outputs and an
internal thermal shutdown.
APPLICATIONS
Total Power Solution for Pentium II processor
application
TYPICAL APPLICATION
5V
Note:
Pentium II is trademark of Intel Corp
IRU3018
SWITCHER1
CONTROL
V
OUT
1
3.3V
LINEAR
CONTROL
LINEAR
REGULATOR
V
OUT
2
V
OUT
3
Figure 1 - Typical application of IRU3018.
PACKAGE ORDER INFORMATION
T
A
(8C)
0 To 70
Rev. 1.6
07/16/02
DEVICE
IRU3018CW
PACKAGE
24-Pin Plastic SOIC WB
www.irf.com
1
IRU3018
ABSOLUTE MAXIMUM RATINGS
V5 Supply Voltage ....................................................
V12 Supply Voltage ..................................................
Storage Temperature Range ......................................
Operating Junction Temperature Range .....................
7V
20V
-65°C To 150°C
0°C To 125°C
PACKAGE INFORMATION
24-PIN WIDE BODY PLASTIC SOIC (W)
TOP VIEW
V12
1
VID4
2
VID3
3
VID2
4
VID1
5
VID0
6
PGood
7
V5
8
SS
9
Fault / Rt
10
Fb2
11
V
IN
2
12
24
UGate1
23
Phase1
22
LGate1
21
PGnd
20
OCSet1
19
V
SEN
1
18
Fb1
17
En
16
Fb3
15
Gate3
14
Gnd
13
V
OUT
2
u
JA
=808C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over V12=12V, V5=5V and T
A
=0 to 70°C. Typical values refer
to T
A
=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
PARAMETER
Supply UVLO Section
UVLO Threshold-12V
UVLO Hysteresis-12V
UVLO Threshold-5V
UVLO Hysteresis-5V
Supply Current
Operating Supply Current
SYM
TEST CONDITION
Supply Ramping Up
Supply Ramping Up
MIN
TYP
10
0.4
4.3
0.3
6
20
MAX
UNITS
V
V
V
V
mA
I
12
I
5
Switching Controllers; Vcore (V
OUT
1)
VID Section
DAC Output Voltage (Note 1)
V
DAC
DAC Output Line Regulation
DAC Output Temp Variation
VID Input LO
VID Input HI
VID Input Internal Pull-Up
Resistor to V5
Error Comparator Section
Input Bias Current
Input Offset Voltage
Delay to Output
Oscillator Section (Internal)
Osc Frequency
V12
V5
0.99Vs
Vs
0.1
0.5
1.01Vs
0.8
2
27
V
%
%
V
V
KV
-2
V
DIFF
=10mV
200
www.irf.com
2
+2
100
mA
mV
ns
KHz
Rev. 1.6
07/16/02
2
IRU3018
PARAMETER
Current Limit Section
CS Threshold Set Current
CS Comp Offset Voltage
Hiccup Duty Cycle
Output Drivers Section
Rise Time
Fall Time
Dead Band Time Between
High Side and Synch Drive
Vcore Switcher Only
2.5V Regulator (V
OUT
2)
Reference Voltage
Reference Voltage
Dropout Voltage
Load Regulation
Line Regulation
Input Bias Current
Output Current
Current Limit
Thermal Shutdown
1.5V Regulator (V
OUT
3)
Reference Voltage
Reference Voltage
Input Bias Current
Output Drive Current
Power Good Section
Core UV Lower Trip Point
Core UV Upper Trip Point
Core UV Hysterises
Core OV Upper Trip Point
Core OV Lower Trip Point
Core OV Hysterises
Fb2 Lower Trip Point
Fb2 Upper Trip Point
Fb3 Lower Trip Point
Fb3 Upper Trip Point
Power Good Output LO
Power Good Output HI
Fault (Overvoltage) Section
Core OV Upper Trip Point
Core OV Lower Trip Point
V
IN
2 Upper Trip Point
V
IN
2 Lower Trip Point
Fault Output HI
Soft-Start Section
Pull-Up Resistor to 5V
Enable Section
En Pin Input LO Voltage
En Pin Input HI Voltage
En Pin Input LO Current
En Pin Input HI Current
SYM
TEST CONDITION
MIN
TYP
200
-5
Css=0.1mF
C
L
=3000pF
C
L
=3000pF
C
L
=3000pF
10
70
70
200
+5
MAX UNITS
mA
mV
%
ns
ns
ns
V
O
2
T
A
=258C, V
OUT
2=Fb2
Io=200mA
1mA< Io <200mA
3.1V<V
IN
2<4V, Vo=2.5V
200
300
1.260
1.260
0.6
0.5
0.2
2
145
V
O
3
T
A
=258C, Gate3=Fb3
1.260
1.260
2
50
V
SEN
1 Ramping Down
V
SEN
1 Ramping Up
V
SEN
1 Ramping Up
V
SEN
1 Ramping Down
Fb2 Ramping Down
Fb2 Ramping Up
Fb3 Ramping Down
Fb3 Ramping Up
R
L
=3mA
R
L
=5K, Pull-Up to 5V
V
SEN
1 Ramping Up
V
SEN
1 Ramping Down
V
IN
2 Ramping Up
V
IN
2 Ramping Down
Io=3mA
OCSet=0V, Phase=5V
V
EN(L)
V
EN(H)
Regulator OFF
Regulator ON
V
EN
=0V to 0.8V
V
EN
=2V to 5V
0.90Vs
0.92Vs
0.02Vs
1.10Vs
1.08Vs
0.02Vs
0.95
1.05
0.95
1.05
0.4
4.8
1.17Vs
1.15Vs
4.3
4.2
10
23
0.8
2
0.01
20
V
V
V
%
%
mA
mA
mA
8C
V
V
mA
mA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
KV
V
V
mA
mA
Note 1:
Vs refers to the set point voltage given in Table 1
Rev. 1.6
07/16/02
www.irf.com
3
IRU3018
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
Table 1 - Set point voltage vs. VID codes
PIN DESCRIPTIONS
PIN#
1
PIN SYMBOL
PIN DESCRIPTION
V12
This pin is connected to the 12V supply and serves as the power Vcc pin for the output
drivers. A high frequency capacitor (typically 1mF) must be placed close to this pin and
PGnd pin and be connected directly from this pin to the ground plane for noise free opera-
tion.
VID4
This pin selects a range of output voltages for the DAC. When in the Low state, the range
is 1.3V to 2.05V and when it switches to Hi state, the range is 2V to 3.5V. This pin is TTL
compatible that realizes a logic “1” as either Hi or Open. When left open, this pin is pulled
up internally by a 27KV resistor to 5V supply.
VID3
MSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic “1” as either Hi or Open. When left open, this pin is pulled up internally by
a 27KV resistor to 5V supply.
VID2
Input to the DAC that programs the output voltage. This pin is TTL compatible that realizes
a logic “1” as either Hi or Open. When left open, this pin is pulled up internally by a 27KV
resistor to 5V supply.
VID1
Input to the DAC that programs the output voltage. This pin is TTL compatible that realizes
a logic “1” as either Hi or Open. When left open, this pin is pulled up internally by a 27KV
resistor to 5V supply.
VID0
LSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic “1” as either Hi or Open. When left open, this pin is pulled up internally by
a 27KV resistor to 5V supply.
PGood
This pin is an open collector output that switches Low when any of the outputs are outside
of the specified under-voltage trip point. It also switches Low when V
SEN
1 pin is more than
10% above DAC voltage setting.
V5
5V supply voltage. A high frequency capacitor (0.1 to 1mF) must be placed close to this
pin and connected from this pin to the ground plane for noise free operation.
SS
This pin provides the soft-start for the switching regulator. An internal resistor charges an
external capacitor that is connected from 5V supply to this pin which ramps up the out-
puts of the switching regulators, preventing the outputs from overshooting as well as
limiting the input current. The second function of the soft-start cap is to provide long off
time (HICCUP) for the synchronous MOSFET during current limiting.
2
3
4
5
6
7
8
9
4
www.irf.com
Rev. 1.6
07/16/02
IRU3018
PIN#
10
PIN SYMBOL
Fault / Rt
PIN DESCRIPTION
This pin has dual function. It acts as an output of the OVP circuitry or it can be used to
program the frequency using an external resistor. When used as a fault detector, if the
switcher output exceeds the OVP trip point, the Fault pin switches to 12V and the soft-
start cap is discharged. If the Fault pin is to be connected to any external circuitry, it
needs to be buffered as shown in the application circuit.
This pin provides the feedback for the internal LDO regulator which its output is V
OUT
4.
This pin is the input that provides power for the internal LDO regulator. It is also monitored
for the under-voltage and over-voltage conditions.
This pin is the output of the internal LDO regulator.
This pin serves as the ground pin and must be connected directly to the ground plane.
This pin controls the gate of an external transistor for the 1.5V GTL+ linear regulator.
This pin provides the feedback for the linear regulator which its output drive is Gate3.
This pin is a TTL compatible Enable pin. When this pin is left open or pulled high, the
device is enabled and when it is pulled low, it will disable the switcher and the LDO
controller (V
OUT
3) leaving the internal 200mA regulator operational. When signal is given to
enable the device, both switcher and V
OUT
3 will go through soft-start, the same as during
start-up.
This pin provides the feedback for the synchronous switching regulator. Typically this pin
can be connected directly to the output of the switching regulator. However, a resistor
divider is recommended to be connected from this pin to V
OUT
1 and Gnd to adjust the
output voltage for any drop in the output voltage that is caused by the trace resistance.
The value of the resistor connected from V
OUT
1 to Fb1 must be less than 100V.
This pin is internally connected to the under-voltage and over-voltage comparators sens-
ing the Vcore status. It must be connected directly to the Vcore supply.
This pin is connected to the Drain of the power MOSFET of the Core supply and it provides
the positive sensing for the internal current sensing circuitry. An external resistor pro-
grams the CS threshold depending on the R
DS
of the power MOSFET. An external capaci-
tor is placed in parallel with the programming resistor to provide high frequency noise
filtering.
This pin serves as the Power ground pin and must be connected directly to the ground
plane close to the source of the synchronous MOSFET. A high frequency capacitor (typi-
cally 1mF) must be connected from V12 pin to this pin for noise free operation.
Output driver for the synchronous power MOSFET for the Core supply.
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
Output driver for the high side power MOSFET for the Core supply.
11
12
13
14
15
16
17
Fb2
V
IN
2
V
OUT
2
Gnd
Gate3
Fb3
En
18
Fb1
19
20
V
SEN
1
OCSet1
21
PGnd
22
23
24
LGate1
Phase1
UGate1
Rev. 1.6
07/16/02
www.irf.com
5
TI技术论坛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
