74ALVCH162827
Rev. 2 — 19 January 2018
20-bit buffer/line driver; non-inverting; with 30 Ω termination
resistors; 3-state
Product data sheet
1
General description
The 74ALVCH162827 20-bit buffers provide high performance bus interface buffering
for wide data/address paths or buses carrying parity. They have NAND output enables
(nOE1 and nOE2) for maximum control flexibility.
The 74ALVCH162827 is designed with 30 Ω series resisters in both the pull-up and pull-
down output structures. This design reduces line noise in applications such as memory
address drivers, clock drivers and bus receivers/transmitters.
To ensure the high impedance state during power up or power down, nOEn should be
tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
The 74ALVCH162827 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2
Features and benefits
•
•
•
•
•
•
•
•
CMOS low power consumption
MultiByte flow-through standard pin-out architecture
Low inductance multiple V
CC
and GND pins for minimum noise and ground bounce
Direct interface with TTL levels (2.7 V to 3.6 V)
Bus hold on data inputs
Current drive ± 12 mA at 3.0 V
Integrated 30 Ω termination resistors
Complies with JEDEC standards:
–
JESD8-5 (2.3 V to 2.7 V)
–
JESD8B/JESD36 (2.7 V to 3.6 V)
•
ESD protection:
–
HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
–
CDM JESD22-C101E exceeds 1000 V
3
Ordering information
Package
Temperature range
Name
TSSOP56
Description
plastic thin shrink small outline package;
56 leads; body width 6.1 mm
Version
SOT364-1
−40 °C to +85 °C
Table 1. Ordering information
Type number
74ALVCH162827DGG
Nexperia
20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state
74ALVCH162827
4
Functional diagram
1
1OE1
56
1OE2
28
2OE1
29
2OE2
55
1A0
1
56
1OE1
1OE2
1Y0
2
42
2A0
28
29
2OE1
2OE2
2Y0
15
2Y1
16
2Y2
17
2Y3
19
2Y4
20
2Y5
21
2Y6
23
2Y7
24
2Y8
26
2Y9
27
aaa-028075
&
&
EN1
EN2
1
1
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
1Y0
1Y1
1Y2
1Y3
1Y4
1Y5
1Y6
1Y7
1Y8
1Y9
2Y0
2Y1
2Y2
2Y3
2Y4
2Y5
2Y6
2Y7
2Y8
2Y9
54
1A1
52
1A2
51
1A3
49
1A4
48
1A5
47
1A6
45
1A7
44
1A8
43
1A9
1Y1
3
41
2A1
1Y2
5
40
2A2
1Y3
6
38
2A3
1Y4
8
37
2A4
1Y5
9
36
2A5
1Y6
10
34
2A6
1Y7
12
33
2A7
1Y8
13
31
2A8
1Y9
14
30
2A9
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
1
2
aaa-028076
Figure 1. Logic symbol
nA0
nA1
nA2
nA3
nA4
nA5
Figure 2. IEC logic symbol
nA6
nA7
nA8
nA9
nOE1
nOE2
nY0
nY1
nY2
nY3
nY4
nY5
nY6
nY7
nY8
nY9
aaa-028077
Figure 3. Logic diagram
V
CC
data input
to internal circuit
mna705
Figure 4. Bus hold circuit
74ALVCH162827
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 2 — 19 January 2018
2 / 14
Nexperia
20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state
74ALVCH162827
5
Pinning information
5.1 Pinning
74ALVCH162827
1OE1
1Y0
1Y1
GND
1Y2
1Y3
V
CC
1Y4
1Y5
1
2
3
4
5
6
7
8
9
56 1OE2
55 1A0
54 1A1
53 GND
52 1A2
51 1A3
50 V
CC
49 1A4
48 1A5
47 1A6
46 GND
45 1A7
44 1A8
43 1A9
42 2A0
41 2A1
40 2A2
39 GND
38 2A3
37 2A4
36 2A5
35 V
CC
34 2A6
33 2A7
32 GND
31 2A8
30 2A9
29 2OE2
aaa-028078
1Y6 10
GND 11
1Y7 12
1Y8 13
1Y9 14
2Y0 15
2Y1 16
2Y2 17
GND 18
2Y3 19
2Y4 20
2Y5 21
V
CC
22
2Y6 23
2Y7 24
GND 25
2Y8 26
2Y9 27
2OE1 28
Figure 5. Pin configuration SOT364-1 (TSSOP56)
74ALVCH162827
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 2 — 19 January 2018
3 / 14
Nexperia
20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state
74ALVCH162827
5.2 Pin description
Table 2. Pin description
Symbol
1A0, 1A1, 1A2, 1A3, 1A4,
1A5, 1A6, 1A7, 1A8, 1A9
2A0, 2A1, 2A2, 2A3, 2A4,
2A5, 2A6, 2A7, 2A8, 2A9
1Y0, 1Y1, 1Y2, 1Y3, 1Y4,
1Y5, 1Y6, 1Y7, 1Y8, 1Y9
2Y0, 2Y1, 2Y2, 2Y3, 2Y4,
2Y5, 2Y6, 2Y7, 2Y8, 2Y9
1OE1, 1OE2, 2OE1, 2OE2
GND
V
CC
Pin
55, 54, 52, 51, 49,
48, 47, 45, 44, 43
42, 41, 40, 38, 37,
36, 34, 33, 31, 30
2, 3, 5, 6, 8,
9, 10, 12, 13, 14
15, 16, 17, 19, 20,
21, 23, 24, 26, 27
1, 56, 28, 29
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
Description
data input
data input
data output
data output
output enable input (active-LOW)
ground (0 V)
positive voltage supply
6
Functional description
Table 3. Function table
X = don’t care; Z = High-impedance OFF-state; H = HIGH voltage level; L = LOW voltage level.
Operating mode
transparent
transparent
High-impedance
Input
nOEn
L
L
H
nAn
L
H
X
Output
nYn
L
H
Z
74ALVCH162827
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 2 — 19 January 2018
4 / 14
Nexperia
20-bit buffer/line driver; non-inverting; with 30 Ω termination resistors; 3-state
74ALVCH162827
7
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
= −40 °C to +85 °C
[2]
[1]
[1]
Conditions
Min
−0.5
−0.5
−0.5
−50
-
-
-
−100
−65
-
Max
+4.6
+4.6
-
±50
±50
100
-
+150
600
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
V
CC
+ 0.5 V
V
I
< 0 V
V
O
> V
CC
or V
O
< 0 V
V
O
= 0 V to V
CC
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP56 packages: above 55 °C derate linearly with 8 mW/K.
8
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
in free air
V
CC
= 2.3 V to 3.0 V
V
CC
= 3.0 V to 3.6 V
Conditions
For maximum speed performance at C
L
= 30 pF
For maximum speed performance at C
L
= 50 pF
Min
2.3
3.0
0
0
−40
0
0
Max
2.7
3.6
V
CC
V
CC
+85
20
10
Unit
V
V
V
V
°C
ns/V
ns/V
Table 5. Recommended operating conditions
Symbol
V
CC
V
I
V
O
T
amb
Δt/ΔV
74ALVCH162827
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 2 — 19 January 2018
5 / 14
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