while covering a wide frequency output range up to
800MHz, without the use of external components.
The high performance and high frequency output is
achieved using a low cost fundamental crystal of
between 19MHz and 40 MHz. The PL685 is
designed to address the demanding requirements of
high performance applications such as Fiber
Channel, serial ATA, Ethernet, SAN, SONET/SDH,
etc.
OUTPUT ENABLE CONTROL
OE Select
(Programmable)
0
1 (Default)
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
BLOCK DIAGRAM
OE/PDB
(Default pre-programmed output path)
XIN/REF
XOUT
Xtal
Osc
PD/CP
LF – HF
LCVCOs
Pre-scalar
4/6
/2
Q
QB
M Divider
(5 bit)
P Divider
(4 bit)
/2
Programmable Function
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 06/24/11 Page 1
(Preliminary)
PL685-88
19MHz to 800MHz Low Phase-Noise XO
PAD ASSIGNMENT
Name
Q
VDD_BUF
QB
VDD_BUF
VDD_DIG
VDD_ANA
XOUT
XIN
SCLK
Pad #
1
2
3
4
5
6
7
8
9
X (m)
1551
1551
1551
1551
1551
1551
1503
630
99
Y (m)
220
448
676
1390
1552
1790
2156
2156
2060
Output buffer
VDD connection for buffer circuitry
Output buffer
VDD connection for buffer circuitry
VDD connection for digital circuitry
VDD connection for analog circuitry
Output connection to crystal
Crystal input connection
The serial interface uses this pin for the serial clock input
(SCLK), during programming.
This pin may be programmed as output enable (OE), or power-
down (PDB) pin.
The serial interface uses this pin for the serial data input (SDIO)
during programming. This pin incorporates an Internal pull -up
resistor of 60KΩ for OE, PDB operations.
Do not connect
GND connection for analog circuitry
GND connection for digital circuitry
GND connection for buffer circuitry
Description
OE/PDB/SDIO
10
99
1256
DNC
GND_ANA
GND_DIG
GND_BUF
11
12
13
14
99
99
99
99
970
700
532
364
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 06/24/11 Page 2
(Preliminary)
PL685-88
19MHz to 800MHz Low Phase-Noise XO
FUNCTIONAL DESCRIPTION
PL685 family of products is an advanced,
programmable LCVCO clock IC that is designed to
meet the most stringent performance specifications
for phase noise, jitter, and power consumption.
There are two main types of VCOs, a) Ring
Oscillator, b) LC Tank oscillator. An LCVCO is made
up of an LC tank oscillator. Although a Ring
Oscillator has very good performance, and has a
good tuning range, its phase noise and jitter
performance, in particular at higher frequencies,
degrades.
On the other hand, an LCVCO has an outstanding
phase noise and jitter performance, even at higher
frequencies. PL685 family of products takes
advantage of this state of the art technology, and
incorporates the LC tank on-chip, for optimal
performance.
PL685 family of products exhibit very low phase
noise/phase jitter and peak to peak jitter, wide
tuning range, and very low-power. All members of
the PL685 family accept a low-cost fundamental
crystal input of 19MHz to 40MHz or a reference
clock input of up to 800MHz and its flexible core is
capable of producing any output frequency between
19MHz to 800MHz.
PLL Programming
The PLL in the PL685 family is fully programmable.
The PLL is equipped with a Prescaler to divide down
the VCO frequency, and a 5-bit VCO frequency
feedback loop divider (M-Counter). The output of the
PLL is transferred to a 4-bit post VCO divider (P-
Counter), to achieve the desired output frequency .
OE (Output Enable)
The OE pin in PL685 family, through programming,
can be configured to support OE pin activation with a
logic ‘1’ or logic ’0’, to provide you with the desired
enable polarity.
OE Select
(Programmable)
0
1 (Default)
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
The OE pin incorporates a 60K
Ω
resistor to either
pull-up or pull-down to the default state when the OE
pin is left open.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 06/24/11 Page 3
(Preliminary)
PL685-88
19MHz to 800MHz Low Phase-Noise XO
ELECTRICAL SPECIFICATIONS
1. ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature (industrial temperature)*
Ambient Operating Temperature (commercial temperature)
Junction Temperature
ESD Protection, Machine Model
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
AI
T
AC
T
J
200
2
-0.5
-0.5
-65
-40
0
MIN
MAX
4.6
V
DD
+0.5
V
DD
+0.5
150
85
70
125
UNITS
V
V
V
C
C
C
C
V
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permane nt damage to the
device and affect product reliability. These co nditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to
commercial grade only.
2. GENERAL ELECTRICAL SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic
Supply Current, Dynamic
PDB Enabled
Output Enable Time
Power Up Time
Operating Voltage
Power Up Ramp Rate
Auto-Calibration Time
Output Clock Duty Cycle
t
OE
T
PU
V
DD
t
PU
t
AC
Time for V
DD
to reach 90% V
DD
.
Power ramp must be monotonic.
At power up
@ V
DD
– 1.3V
SYMBOL
I
DDQ
CONDITIONS
LVPECL, 622.08MHz, 3.3V
PDB = 0, 3.3V
OE logic 0 to logic 1, Ta=25º C.
Add one clock period to this
measurement for a usable clock
output.
PDB logic 0 to logic 1, Ta=25º C
2.97
0.1
3.3
MIN
TYP
MAX
90
10
50
10
3.63
100
10
45
50
55
UNITS
mA
uA
ns
ms
V
ms
ms
%
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 06/24/11 Page 4
(Preliminary)
PL685-88
19MHz to 800MHz Low Phase-Noise XO
4. CRYSTAL SPECIFICATIONS
PARAMETERS
Crystal Resonator Frequency
Crystal Cload
Shunt Capacitance
Recommended ESR
SYMBOL
F
XIN
C
L_ Crys ta l
C
0_ Crys ta l
R
E
AT cut
CONDITIONS
Parallel Fundamental Mode
V
DD
= 3.3V, programmable
MIN
19
8
TYP
MAX
40
12
3.5
50
UNITS
MHz
pF
pF
Ω
5. JITTER SPECIFICATIONS
PARAMETERS
RMS Phase Jitter
Period Jitter, Pk-to-Pk
FREQUENCY
622.08MHz
622.08MHz
CONDITIONS
10kHz to 20MHz, XIN=38.88MHz
10K cycles, XIN=38.88MHz
MIN
TYP
0.5
30
MAX
UNITS
ps
ps
6. PHASE NOISE SPECIFICATIONS
Freq.
@
PARAMETERS
(MHz)
10Hz
Phase Noise, relative
to carrier (typical)
155.52
622.08
-58
-56
@
100Hz
-95
-87
@
1KHz
-119
-106
@
@
10KHz 100KHz
-124
-111
-129
-115
@
1MHz
135
-125
@
10MHz
148
-145
UNITS
dBc/Hz
7. LVPECL OUTPUTS (Q, QB)
PARAMETERS
Output High Voltage
Output Low Voltage
Output Frequency
Output Rise, Fall Times
Output Voltage Swing
LVPECL Levels Test Circuit
OUT
VDD
OUT
45 - 55%
50?
2.0V
50%
OUT
80%
50?
OUT
OUT
t
SKEW
20%
OUT
t
R
t
F
50%
SYMBOL
V
OH
V
OL
F
ou t
t
r
, t
f
V
pp
CONDITIONS
Q, QB
Standard LVPECL Termination,
V
DD
= 3.3V
3.3V
20% - 80% of Q
pp
/QB
p p
Q, QB
MIN
2.275
1.490
19
550
TYP
2.350
1.600
200
800
DUTY CYCLE
MAX
2.420
1.680
800
300
900
UNITS
V
V
MHz
ns
mV
LVPECL Output Skew
LVPECL Transistion Time Waveform
55 - 45%
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
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