NL3S22S
USB 2.0 + Audio Switch
The NL3S22S is a double−pole/double−throw (DPDT) analog
switch for routing high speed differential data and audio. The
high−speed data path is compliant with High Speed USB 2.0, Full
Speed USB 1.1, Low Speed USB 1.0 and any generic UART protocol.
The multi−purpose audio path is capable of passing signals with
negative voltages as low as 2 V below ground and features shunt
resistors to reduce Pop and Click noise in the audio system.
Features
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V
CC
Range: 2.7 V to 5.5 V
Control Pins Compatible with 1.8 V Interfaces
I
CC
: 23
mA
(Typ)
ESD Performance: 4 kV HBM
Available in1.4 mm x 1.8 mm UQFN10
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Input Signal Range: 0 V to 3.7 V
R
DS(on)
: 5
W
(Typ)
C
ON
: 4.5 pF (Typ)
Data Rate: USB 2.0–Compliant – up to 480 Mbps
Input Signal Range:
−2.0
V to 2.0 V
R
DSON
: 3
W
(Typ)
R
ON(FLAT)
: 0.002
W
(Typ)
THD: 0.002% (R
L
= 16
W
/ V
IS
= 0.4 V
RMS
)
Smartphones
Tablets
USB 2.0 Hosts/Peripherals
Audio / High−Speeds Data Switching
MARKING
DIAGRAM
UQFN10
CASE 488AT
AW MG
G
1
AW
M
G
=
=
=
Device Code
Date Code
Pb−Free Device
High Speed Data Path
(Note: Microdot may be in either location)
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ORDERING INFORMATION
Device
NL3S22SMUTAG
Package
UQFN10
(Pb−Free)
Shipping
†
3000 / Tape &
Reel
Audio Path
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Applications
©
Semiconductor Components Industries, LLC, 2016
October, 2016
−
Rev. 0
1
Publication Order Number:
NL3S22S/D
NL3S22S
V
CC
HDP
D+
AUDP
Shunt
HDN
D−
AUDN
Shunt
EN
SEL
Control Logic
GND
Figure 1. Block Diagram
FUNCTION TABLE
EN
0
1
1
SEL
X
0
1
Shunt Status
ON
OFF
ON
D+/D− Function
No Connect
AUDP/AUDN
HDP/HDN
Figure 2. UQFN10 – Top Through View
PIN DESCRIPTION
Pin Name
V
CC
HDN
AUDN
SEL
D−
GND
D+
EN
AUDP
HDP
Pin
1
2
3
4
5
6
7
8
9
10
Power Supply
High Speed Differential Data (−)
Audio Signal (−)
Function Select
Audio/Data Common I/O (−)
Ground
Audio/Data Common I/O (+)
Chip Enable
Audio Signal (+)
High Speed Differential Data (+)
Description
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2
NL3S22S
MAXIMUM RATINGS
Rating
V
CC
V
IS
Positive DC Supply Voltage
Analog Input/Output Voltage
HDP, HDN
AUDP, AUDN
D+, D−
V
IN
T
s
T
L
T
J
MSL
I
LU
ESD
Digital Control Pin Voltage on EN, SEL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 seconds
Junction Temperature Under Bias
Moisture Sensitivity (Note 1)
Latchup Current (Note 2)
ESD Protection (Note 3)
Human Body Model
Symbol
Value
−0.3
to +6
−0.3
to +5.5
−2.5
to V
CC
+ 0.3
−2.5
to +5.5
−0.3
to V
CC
+ 0.3
−55
to +150
260
150
Level 1
±100
4000
mA
V
V
°C
°C
°C
Unit
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
2. Latch up Current Maximum Rating:
±100
mA per JEDEC standard: JESD78.
3. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM)
±4.0
kV per JEDEC standard: JESD22−A114 for all pins.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CCEN
V
IS
Positive DC Supply Voltage
Switch Input / Output Voltage (Note 4)
HDP, HDN
AUDP, AUDN
D+, D−
V
IN
T
A
Digital Control Input Voltage
Operating Temperature Range
Parameter
Min
2.7
0
−2.0
−2.0
GND
−40
Max
5.5
3.7
2.0
3.7
V
CC
+85
V
°C
Unit
V
V
4. f the audio channel is not in use, it is recommended that no signals are applied on the audio inputs AUDN and AUDP.
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3
NL3S22S
DC ELECTRICAL CHARACTERISTICS
(Typical values are at V
CC
= +3.6 V and T
A
= +25
⁰C)
−40
⁰C
to 85
⁰C
Symbol
POWER SUPPLY
I
CC
V
IH
Supply Current
I
IS
= 0 mA
4.2
−
23
105
mA
V
Parameter
Test Conditions
V
CC
(V)
Min
Typ
Max
Unit
Control Logic (EN, SEL)
Input High Voltage
4.2
3.6
2.7
V
IL
Input Low Voltage
4.2
3.6
2.7
V
IHYS
I
IN
R
ON
DR
ON
R
FLAT(ON)
R
SH
R
ON
DR
ON
R
FLAT(ON)
I
SW(OFF)
I
SW(ON)
Input Hysteresis
Leakage Current
2.7 – 5.5
2.7 – 5.5
1.5
1.4
1.3
−
−
−
−
−
−
−
−
−
−
−
250
−
−
−
−
0.4
0.4
0.4
−
±150
mV
nA
V
AUDIO SWITCH (AUDP/AUDN
e
D+/D−)
ON−Resistance
ON−Resistance Matching
Between Channels
ON Resistance Flatness
Shunt Resistance
V
IS
=
−2.0
V to 2.0 V, I
IS
= 50 mA
V
IS
=
−2.0
V to 2.0 V, I
IS
= 50 mA
V
IS
=
−2.0
V to 2.0 V, I
IS
= 50 mA
3.0
3.0
3.0
3.6
−
−
−
−
3
0.05
0.002
125
5
−
−
200
W
W
W
W
DATA SWITCH (HDP/HDN
e
D+/D−)
ON−Resistance
ON−Resistance Matching
Between Channels
ON Resistance Flatness
OFF−State Leakage
ON−State Leakage
V
IS
= 0 V to 1.7 V, I
IS
= 15 mA
V
IS
= 0 V to 1.7 V, I
IS
= 15 mA
V
IS
= 0 V to 1.7 V, I
IS
= 15 mA
V
IS
= 0 V to 3.6
V
IS
= 0 V to 3.6
3.0
3.0
3.0
3.6
3.6
−
−
−
−
−
5
0.02
0.003
−
−
7.5
−
−
200
±200
W
W
W
nA
nA
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NL3S22S
AC ELECTRICAL CHARACTERISTICS
(Typical values are at V
CC
= +3.6 V and T
A
= +25
⁰C)
−40
⁰C
to 85
⁰C
Symbol
Parameter
Test Conditions
V
CC
(V)
2.7 – 5.5
2.7 – 5.5
Min
Typ
Max
Unit
AUDIO SWITCH (AUDP/AUDN
e
D+/D−)
THD
PSRR
Audio THD
Power Supply Ripple
Rejection
f = 20 Hz to 20 kHz, V
IS
= 0.4 V
RMS
,
DC Bias = 0 V, R
L
= 16
W
From V
CC
unto AUDP/AUDN,
f = 217 Hz, R
L
= 16
W
−
−
0.002
118
−
−
%
dB
DATA SWITCH (HDP/HDN
e
D+/D−)
C
ON
C
OFF
D
IL
Equivalent
ON−Capacitance
Equivalent
OFF−Capacitance
Differential Insertion
Loss
Switch ON, f = 1 MHz
Switch OFF, f = 1 MHz
f = 10 MHz
f = 800 MHz
f = 1.1 GHz
D
ISO
Differential Off−Isolation
f = 10 MHz
f = 800 MHz
f = 1.1 GHz
D
CTK
Differential Crosstalk
f = 10 MHz
f = 800 MHz
f = 1.1 GHz
PSRR
Power Supply Ripple
Rejection
From V
CC
unto D+/D−,
f = 217 Hz, R
L
= 50
W
3.6
3.6
2.7 – 5.5
2.7 – 5.5
2.7 – 5.5
2.7 – 5.5
2.7 – 5.5
2.7 – 5.5
2.7 – 5.5
2.7 – 5.5
2.7 – 5.5
2.7 – 5.5
−
−
−
−
−
−
−
−
−
−
−
−
4.84
2.06
−0.42
−1.89
−3.01
−60
−15
−15
−67
−23
−19
108
−
−
−
−
−
−
−
−
−
−
−
−
dB
dB
dB
pF
pF
dB
DYNAMIC TIMING
t
PD
t
ON
Propagation Delay
(Notes 5 and 6)
Turn−On Time
V
NOn
or V
NCn
= 0V, R
L
= 50
W,
V
IS
= 1 V, R
L
= 50
W,
C
L
= 7 pF (fix-
ture only)
EN or SEL to AUDP/AUDN
EN or SEL to HDP/HDN
t
OFF
Turn−Off Time
V
IS
= 1 V, R
L
= 50
W,
C
L
= 7 pF (fix-
ture only)
EN or SEL to AUDP/AUDN
EN or SEL to HDP/HDN
t
sk(b−b)
t
sk(ch−ch)
Bit to bit skew
Channel to channel skew
Within the same differential channel
Maximum skew between all chan-
nels
2.7 – 5.5
2.7 – 5.5
2.7 – 5.5
−
−
−
−
67
1200
5
5
−
−
−
−
ps
ps
2.7 – 5.5
2.7 – 5.5
−
−
2.2
6.2
−
−
ns
−
0.25
−
ns
ms
5. Guaranteed by design.
6. No other delays than the RC network formed by the load resistance and the load capacitance of the switch are added on the bus. For a 10
pF load, this delay is 5 ns which is much smaller than rise and fall time of typical driving systems. Propagation delays on the bus are
determined by the driving circuit on the driving side and its interactions with the load of the driven side.
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