74HC4094-Q100;
74HCT4094-Q100
Rev. 2 — 14 November 2018
8-stage shift-and-store bus register
Product data sheet
1. General description
The 74HC4094-Q100; 74HCT4094-Q100 is an 8-bit serial-in/serial or parallel-out shift register with
a storage register and 3-state outputs. Both the shift and storage register have separate clocks.
The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading.
Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the
LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same
data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading
when clock edges are slow. The data in the shift register is transferred to the storage register
when the STR input is HIGH. Data in the storage register appears at the outputs whenever the
output enable input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance
OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of
V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
•
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
•
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Complies with JEDEC standard JESD7A
Input levels:
•
For 74HC4094-Q100: CMOS level
•
For 74HCT4094-Q100: TTL level
Low-power dissipation
ESD protection:
•
MIL-STD-883, method 3015 exceeds 2000 V
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 Ω)
•
•
3. Applications
•
•
Serial-to-parallel data conversion
Remote control holding register
Nexperia
74HC4094-Q100; 74HCT4094-Q100
8-stage shift-and-store bus register
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74HC4094D-Q100
74HCT4094D-Q100
74HC4094DB-Q100
74HCT4094DB-Q100
74HC4094PW-Q100
-40 °C to +125 °C
TSSOP16
-40 °C to +125 °C
SSOP16
-40 °C to +125 °C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
5. Functional diagram
3
CP
1
STR
QS1
QS2
QP0
QP1
2
D
QP2
QP3
QP4
QP5
QP6
OE
15
QP7
9
10
4
5
6
7
14
13
12
11
3
2
1
15
C2
EN3
SRG8
C1/
1D
2D
3
4
5
6
7
14
13
12
11
9
10
001aaf111
001aaf112
Fig. 1.
Logic symbol
2
3
D
CP
Fig. 2.
8-STAGE SHIFT
REGISTER
IEC Logic symbol
QS2
QS1
10
9
1
STR
8-BIT STORAGE
REGISTER
15
OE
3-STATE OUTPUTS
QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7
4
5
6
7
14
13
12
11
001aaf119
Fig. 3.
Functional diagram
74HC_HCT4094_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 2 — 14 November 2018
2 / 19
Nexperia
74HC4094-Q100; 74HCT4094-Q100
8-stage shift-and-store bus register
STAGE 0
D
D
CP
FF 0
CP
D
LE
LATCH 0
STR
OE
Q
CP
Q
D
STAGES 1 TO 6
Q
STAGE 7
D
CP
FF 7
D
LE
LATCH
D
LE
LATCH 7
Q
Q
QS2
Q
QS1
QP0
QP1
QP2
QP3
QP4
QP5
QP6
QP7
001aag799
Fig. 4.
Logic diagram
6. Pinning information
6.1. Pinning
74HC4094
74HCT4094
STR
D
CP
QP0
QP1
QP2
QP3
GND
1
2
3
4
5
6
7
8
001aan577
16 V
CC
15 OE
14 QP4
13 QP5
12 QP6
11 QP7
10 QS2
9
QS1
STR
D
CP
QP0
QP1
QP2
QP3
GND
1
2
3
4
5
6
7
8
74HC4094
74HCT4094
16 V
CC
15 OE
14 QP4
13 QP5
12 QP6
11 QP7
10 QS2
9
001aan578
QS1
Fig. 5.
Pin configuration SOT109-1 (SO16)
Fig. 6.
Pin configuration SOT338-1 (SSOP16) and
SOT403-1 (TSSOP16)
74HC_HCT4094_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 2 — 14 November 2018
3 / 19
Nexperia
74HC4094-Q100; 74HCT4094-Q100
8-stage shift-and-store bus register
6.2. Pin description
Table 2. Pin description
Symbol
STR
D
CP
QP0 to QP7
GND
QS1, QS2
OE
V
CC
Pin
1
2
3
4, 5, 6, 7, 14, 13, 12, 11
8
9, 10
15
16
Description
strobe input
data input
clock input
parallel output
ground supply voltage
serial output
output enable input
supply voltage
7. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = HIGH-impedance OFF-state; NC = no change;
↑ = positive-going transition; ↓ = negative-going transition;
Q6S = the data in register stage 6 before the LOW to HIGH clock transition;
Q7S = the data in register stage 7 before the HIGH to LOW clock transition.
Inputs
CP
↑
↓
↑
↑
↑
↓
OE
L
L
H
H
H
H
STR
X
X
L
H
H
H
CLOCK INPUT
DATA INPUT
STROBE INPUT
OUTPUT ENABLE INPUT
INTERNAL Q0S (FF 0)
OUTPUT QP0
INTERNAL Q6S (FF 6)
OUTPUT QP6
SERIAL OUTPUT QS1
SERIAL OUTPUT QS2
001aaf117
Parallel outputs
D
X
X
X
L
H
H
QP0
Z
Z
NC
L
H
NC
QPn
Z
Z
NC
QPn -1
QPn -1
NC
Serial outputs
QS1
Q6S
NC
Q6S
Q6S
Q6S
NC
QS2
NC
Q7S
NC
NC
NC
Q7S
Z-state
Z-state
At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the
QSn outputs.
Fig. 7.
Timing diagram
74HC_HCT4094_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 2 — 14 November 2018
4 / 19
Nexperia
74HC4094-Q100; 74HCT4094-Q100
8-stage shift-and-store bus register
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V
V
O
= -0.5 V to (V
CC
+ 0.5 V)
Min
-0.5
-
-
-
-
-
-65
Max
+7
±20
±20
±25
+50
-50
+150
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
SO16, SSOP16 and TSSOP16 packages
[1]
-
For SO16: P
tot
derates linearly with 8 mW/K above 70 °C.
For SSOP16 and TSSOP16 packages: P
tot
derates linearly with 5.5 mW/K above 60 °C.
9. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC4094-Q100
Min
2.0
0
0
-40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT4094-Q100
Min
4.5
0
0
-40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
°C
ns/V
ns/V
ns/V
Unit
74HC_HCT4094_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 2 — 14 November 2018
5 / 19
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
