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DRV8701
SLVSCX5B – MARCH 2015 – REVISED JULY 2015
DRV8701 Brushed DC Motor Full-Bridge Gate Driver
1 Features
1
2 Applications
•
•
•
•
•
•
Industrial Brushed-DC Motors
Robotics
Home Automation
Industrial Pumps and Valves
Power Tools
Handheld Vacuum Cleaners
•
•
•
•
•
•
•
•
•
•
•
Single H-Bridge Gate Driver
– Drives Four External N-Channel MOSFETs
– Supports 100% PWM Duty Cycle
5.9-V to 45-V Operating Supply Voltage Range
Two Control Interface Options
– PH/EN (DRV8701E)
–
PWM
(DRV8701P)
Adjustable Gate Drive (5 Levels)
– 6-mA to 150-mA Source Current
– 12.5-mA to 300-mA Sink Current
Supports 1.8-V, 3.3-V, and 5-V Logic Inputs
Current Shunt Amplifier (20 V/V)
Integrated PWM Current Regulation
– Limits Motor Inrush Current
Low-Power Sleep Mode (9
μA)
Two LDO Voltage Regulators to Power External
Components
– AVDD: 4.8 V, up to 30-mA Output Load
– DVDD: 3.3 V, up to 30-mA Output Load
Small Package and Footprint
– 24-Pin VQFN (PowerPAD™)
– 4.0 × 4.0 × 0.9 mm
Protection Features:
– VM Undervoltage Lockout (UVLO)
– Charge Pump Undervoltage (CPUV)
– Overcurrent Protection (OCP)
– Pre-Driver Fault (PDF)
– Thermal Shutdown (TSD)
– Fault Condition Output (nFAULT)
3 Description
The DRV8701 is a single H-bridge gate driver that
uses four external N-channel MOSFETs targeted to
drive a 12-V to 24-V bidirectional brushed DC motor.
A PH/EN (DRV8701E) or PWM (DRV8701P)
interface allows simple interfacing to controller
circuits. An internal sense amplifier allows for
adjustable current control. The gate driver includes
circuitry to regulate the winding current using fixed
off-time PWM current chopping.
DRV8701 drives both high- and low-side FETs with
9.5-V V
GS
gate drive. The gate drive current for all
external FETs is configurable with a single external
resistor on the IDRIVE pin.
A low-power sleep mode is provided which shuts
down internal circuitry to achieve very-low quiescent
current draw. This sleep mode can be set by taking
the nSLEEP pin low.
Internal
protection
functions
are
provided:
undervoltage
lockout,
charge
pump
faults,
overcurrent
shutdown,
short-circuit
protection,
predriver faults, and overtemperature. Fault
conditions are indicated on the nFAULT pin.
Device Information
(1)
PART NUMBER
DRV8701
PACKAGE
VQFN (24)
BODY SIZE (NOM)
4.00 × 4.00 x 0.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACE
Simplified System Block Diagram
5.9V to 45 V
Gate-Drive Current
t
DRIVE
I
DRIVE,SNK
High-side
gate drive
current
High-side
V
GS
I
HOLD
I
STRONG
I
DRIVE,SRC
I
HOLD
I
HOLD
DRV8701
PH/EN or PWM
nSLEEP
VREF
Controller
sense output
nFAULT
H-Bridge Gate
Driver
Shunt Amp
Protection
LDO
Gate
drive
FETs
M
t
DRIVE
I
DRIVE,SNK
sense
Low-side
gate drive
current
Low-side
V
GS
I
HOLD
I
HOLD
I
STRONG
I
DRIVE,SRC
I
HOLD
3.3 & 4.8 V
30 mA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8701
SLVSCX5B – MARCH 2015 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features
..................................................................
Applications
...........................................................
Description
.............................................................
Revision History.....................................................
Pin Configuration and Functions
.........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
1
1
1
2
3
5
5
5
5
6
7
9
7.4 Device Functional Modes........................................
26
8
Application and Implementation
........................
28
8.1 Application Information............................................
28
8.2 Typical Applications ...............................................
28
9
Power Supply Recommendations......................
32
9.1 Bulk Capacitance Sizing .........................................
32
10 Layout...................................................................
33
10.1 Layout Guidelines .................................................
33
10.2 Layout Example ....................................................
33
11 Device and Documentation Support
.................
34
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
34
34
34
7
Detailed Description
............................................
12
7.1 Overview .................................................................
12
7.2 Functional Block Diagram .......................................
13
7.3 Feature Description.................................................
14
12 Mechanical, Packaging, and Orderable
Information
...........................................................
34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2015) to Revision B
•
Page
Updated test conditions for I
DRIVE,SNK
and corrected TYP values ...........................................................................................
8
Page
Changes from Original (March 2015) to Revision A
•
Updated device status to production data .............................................................................................................................
1
2
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DRV8701
Copyright © 2015, Texas Instruments Incorporated
DRV8701
www.ti.com
SLVSCX5B – MARCH 2015 – REVISED JULY 2015
5 Pin Configuration and Functions
RGE Package
24-Pin VQFN
DRV8701E Top View
RGE Package
24-Pin VQFN
DRV8701P Top View
GH2
SH2
GL2
SP
SN
GL1
24
23
22
21
20
19
24
23
22
21
20
VM
VCP
CPH
CPL
GND
VREF
1
2
3
4
5
6
10
11
12
7
8
9
18
17
GND
(PPAD)
16
15
14
13
SH1
GH1
GND
PH
EN
nSLEEP
VM
VCP
CPH
CPL
GND
VREF
19
GH2
SH2
GL2
SP
SN
GL1
1
2
3
4
5
6
10
11
12
7
8
9
18
17
GND
(PPAD)
16
15
14
13
SH1
GH1
GND
IN1
IN2
nSLEEP
AVDD
DVDD
nFAULT
SNSOUT
SO
IDRIVE
AVDD
DRV8701E (PH/EN)
DESCRIPTION
PIN
NAME
EN
PH
NO.
14
15
TYPE
Input
Input
Bridge enable input
Bridge phase input
Logic low places the bridge in brake mode; see
Table 1
Controls the direction of the H-bridge; see
Table 1
DRV8701P (PWM)
PIN
NAME
IN1
IN2
NO.
15
14
TYPE
Input
Input
Bridge PWM input
DESCRIPTION
Logic controls the state of H-bridge; see
Table 2
Common Pins
PIN
NAME
VM
NO.
1
5
GND
VCP
CPH
CPL
DVDD
AVDD
nSLEEP
IDRIVE
16
PPAD
2
3
4
8
7
13
12
Power
Power
Power
Power
Input
Input
Charge pump output
Charge pump switching nodes
Logic regulator
Analog regulator
Device sleep mode
Gate drive current setting pin
Connect a 16-V, 1-µF ceramic capacitor to VM
Connect a 0.1-µF X7R capacitor rated for VM between CPH and
CPL
3.3-V logic supply regulator; bypass to GND with a 6.3-V, 1-µF
ceramic capacitor
4.8-V analog supply regulator; bypass to GND with a 6.3-V, 1-µF
ceramic capacitor
Pull logic low to put device into a low-power sleep mode with FETs
High-Z; internal pulldown
Resistor value or voltage forced on this pin sets the gate drive
current; see applications section for more details
Power
Device ground
Must be connected to ground
TYPE
DESCRIPTION
Connect to motor supply voltage; bypass to GND with a 0.1-µF
ceramic plus a 10-µF minimum capacitor rated for VM; additional
capacitance may be required based on drive current
Power
Power supply
DVDD
nFAULT
SNSOUT
SO
IDRIVE
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Product Folder Links:
DRV8701
DRV8701
SLVSCX5B – MARCH 2015 – REVISED JULY 2015
www.ti.com
Common Pins (continued)
PIN
NAME
VREF
nFAULT
SNSOUT
SO
SN
SP
GH1
GH2
GL1
GL2
SH1
SH2
NO.
6
9
10
11
20
21
17
24
19
22
18
23
TYPE
Input
Open
Drain
Open
Drain
Output
Input
Input
Output
Output
Input
Analog reference input
Fault indication pin
Sense comparator output
Shunt amplifier output
Shunt amplifier negative input
Shunt amplifier positive input
High-side gate
Low-side gate
Phase node
DESCRIPTION
Controls the current regulation; apply a voltage between 0.3 V and
AVDD
Pulled logic low with fault condition; open-drain output requires an
external pullup
Pulled logic low when the drive current hits the current chopping
threshold; open-drain output requires an external pullup
Voltage on this pin is equal to the SP voltage times A
V
plus an
offset; place no more than 1 nF of capacitance on this pin
Connect to SP through current sense resistor and to GND
Connect to low-side FET source and to SN through current sense
resistor
Connect to high-side FET gate
Connect to low-side FET gate
Connect to high-side FET source and low-side FET drain
External Passive Components
COMPONENT
C
VM1
C
VM2
C
VCP
C
SW
C
DVDD
C
AVDD
R
IDRIVE
R
nFAULT
R
SNSOUT
R
SENSE
(1)
VM
VM
VCP
CPH
DVDD
AVDD
IDRIVE
VCC
(1)
VCC
(1)
SP
PIN 1
GND
GND
VM
CPL
GND
GND
GND
nFAULT
SNSOUT
SN/GND
PIN 2
RECOMMENDED
0.1-µF ceramic capacitor rated for VM
≥10-µF
capacitor rated for VM
16-V, 1-µF ceramic capacitor
0.1-µF X7R capacitor rated for VM
6.3-V, 1-µF ceramic capacitor
6.3-V, 1-µF ceramic capacitor
See
Typical Applications
for resistor sizing
≥10-kΩ
pullup
≥10-kΩ
pullup
Optional low-side sense resistor
VCC is not a pin on the DRV8701, but a VCC supply voltage pullup is required for open-drain outputs nFAULT and SNSOUT. The
system controller supply can be used for this pullup voltage, or these pins can be pulled up to either AVDD or DVDD.
External FETs
Component
Q
HS1
Q
LS1
Q
HS2
Q
LS2
Gate
GH1
GL1
GH2
GL2
Drain
VM
SH1
VM
SH2
Source
SH1
SP or GND
SH2
SP or GND
Supports up to 200-nC FETs at 40-kHz PWM; see
Detailed Design Procedure
for more details
Recommended
4
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Product Folder Links:
DRV8701
Copyright © 2015, Texas Instruments Incorporated
DRV8701
www.ti.com
SLVSCX5B – MARCH 2015 – REVISED JULY 2015
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range referenced with respect to GND (unless otherwise noted)
MIN
Power supply voltage (VM)
Power supply voltage ramp rate (VM)
Charge pump voltage (VCP, CPH)
Charge pump negative switching pin (CPL)
Internal logic regulator voltage (DVDD)
Internal analog regulator voltage (AVDD)
Control pin voltage (PH, EN, IN1, IN2, nSLEEP, nFAULT, VREF, IDRIVE, SNSOUT)
High-side gate pin voltage (GH1, GH2)
Continuous phase node pin voltage (SH1, SH2)
Pulsed 10 µs phase node pin voltage (SH1, SH2)
Low-side gate pin voltage (GL1, GL2)
Continuous shunt amplifier input pin voltage (SP, SN)
Pulsed 10-µs shunt amplifier input pin voltage (SP, SN)
Shunt amplifier output pin voltage (SO)
Open-drain output current (nFAULT, SNSOUT)
Gate pin source current (GH1, GL1, GH2, GL2)
Gate pin sink current (GH1, GL1, GH2, GL2)
Shunt amplifier output pin current (SO)
Operating junction temperature, T
J
Storage temperature, T
stg
(1)
–0.3
0
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–1.2
–2.0
–0.3
–0.5
–1
–0.3
0
0
0
0
–40
–65
(1)
MAX
47
2
VM + 12
VM
3.8
5.75
5.75
VM + 12
VM + 1.2
VM + 2
12
1
1
5.75
10
250
500
5
150
150
UNIT
V
V/µs
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
°C
°C
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended
Operating Conditions.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V
(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM) ESD stress voltage
(1)
Charged device model (CDM) ESD stress voltage
(2)
±2000
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VM
VCC
VREF
ƒ
PWM
I
AVDD
I
DVDD
I
SO
T
A
(1)
(2)
Power supply voltage range
Logic level input voltage
Reference RMS voltage range (VREF)
Applied PWM signal (PH/EN or IN1/IN2)
AVDD external load current
DVDD external load current
Shunt amplifier output current loading (SO)
Operating ambient temperature
Operational at VREF = 0 to 0.3 V, but accuracy is degraded
Power dissipation and thermal limits must be observed
–40
5.9
0
0.3
(1)
MAX
45
5.5
AVDD
100
30
(2)
30
(2)
5
125
UNIT
V
V
V
kHz
mA
mA
mA
°C
Copyright © 2015, Texas Instruments Incorporated
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