74LVC1G99
Ultra-configurable multiple function gate; 3-state
Rev. 10.1 — 22 October 2018
Product data sheet
1. General description
The 74LVC1G99 provides a low voltage, ultra-configurable, multiple function gate with 3-state
output. The device can be configured as one of several logic functions including, AND, OR,
NAND, NOR, XOR, XNOR, inverter, buffer and MUX. No external components are required to
configure the device as all inputs can be connected directly to V
CC
or GND. The 3-state output is
controlled by the output enable input (OE). A HIGH level at OE causes the output (Y) to assume a
high-impedance OFF-state. When OE is LOW, the output state is determined by the signals applied
to the Schmitt trigger inputs (A, B, C and D).
Due to the use of Schmitt trigger inputs the device is tolerant of slowly changing input signals,
transforming them into sharply defined, jitter free output signals. By eliminating leakage current
paths to V
CC
and GND, the inputs and disabled output are also over-voltage tolerant, making the
device suitable for mixed-voltage applications.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry
disables the output, preventing the damaging backflow current through the device when it is
powered down.
The 74LVC1G99 is fully specified over the supply range from 1.65 V to 5.5 V.
2. Features and benefits
•
•
•
•
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
•
JESD8-7 (1.65 V to 1.95 V)
•
JESD8-5 (2.3 V to 2.7 V)
•
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V
±24 mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C.
•
•
•
•
•
•
•
•
Nexperia
74LVC1G99
Ultra-configurable multiple function gate; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74LVC1G99DP
74LVC1G99GT
74LVC1G99GF
74LVC1G99GM
74LVC1G99GN
74LVC1G99GS
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
Name
TSSOP8
XSON8
XSON8
XQFN8
XSON8
XSON8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
Version
SOT505-2
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 × 1 × 0.5 mm
plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 × 1.6 × 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2 × 1.0 × 0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 × 1.0 × 0.35 mm
SOT1089
SOT902-2
SOT1116
SOT1203
4. Marking
Table 2. Marking codes
Type number
74LVC1G99DP
74LVC1G99GT
74LVC1G99GF
74LVC1G99GM
74LVC1G99GN
74LVC1G99GS
[1]
Marking code
[1]
V99
V99
YF
V99
YF
YF
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
OE
A
B
C
D
Y
001aah322
Fig. 1.
Logic symbol
74LVC1G99
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 10.1 — 22 October 2018
2 / 26
Nexperia
74LVC1G99
Ultra-configurable multiple function gate; 3-state
6. Pinning information
6.1. Pinning
74LVC1G99
OE
1
8
V
CC
A
2
7
Y
74LVC1G99
OE
A
B
GND
1
2
3
4
001aah323
B
8
7
6
5
V
CC
Y
D
C
3
6
D
GND
4
5
C
001aah324
Transparent top view
Fig. 2.
Pin configuration SOT505-2 (TSSOP8)
terminal 1
index area
Y
1
Fig. 3.
74LVC1G99
V
CC
Pin configuration SOT833-1, SOT1089, SOT1116
and SOT1203 (XSON8)
8
7
OE
D
2
6
A
GND
4
C
3
5
B
001aah325
Transparent top view
Fig. 4.
Pin configuration SOT902-2 (XQFN8)
6.2. Pin description
Table 3. Pin description
Symbol
Pin
SOT505-2, SOT833-1, SOT1089,
SOT1116 and SOT1203
OE
A
B
GND
C
D
Y
V
CC
1
2
3
4
5
6
7
8
SOT902-2
7
6
5
4
3
2
1
8
output enable input OE (active LOW)
data input
data input
ground (0 V)
data input
data input
data output
supply voltage
Description
74LVC1G99
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 10.1 — 22 October 2018
3 / 26
Nexperia
74LVC1G99
Ultra-configurable multiple function gate; 3-state
7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Input
OE
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
Output
Y
L
H
L
H
L
L
H
H
H
L
H
L
H
H
L
L
Z
7.1. Logic configurations
Table 5. Function selection table
Primary function
3-state buffer
3-state inverter
3-state 2-input multiplexer
3-state 2-input multiplexer with inverting output
3-state 2-input AND
3-state 2-input AND with one inverting input
3-state 2-input AND with two inverting inputs
3-state 2-input NAND
3-state 2-input NAND with one inverting input
3-state 2-input NAND with two inverting inputs
3-state 2-input XOR
3-state 2-input XNOR
3-state 2-input XOR with one inverting input
3-state 2-input NOR with two inverting inputs
3-state 2-input NOR with one inverting input
3-state 2-input NOR
3-state 2-input OR with two inverting inputs
3-state 2-input OR with one inverting input
3-state 2-input OR
Complementary function
74LVC1G99
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 10.1 — 22 October 2018
4 / 26
Nexperia
74LVC1G99
Ultra-configurable multiple function gate; 3-state
7.2. 3-state buffer functions available
Table 6. Function table
H = HIGH voltage level; L = LOW voltage level; See
Fig. 5.
Function
3-state buffer
Input
OE
L
L
L
L
L
L
L
A
input
H or L
L
H
H
H or L
L
OE
input
Y
001aah326
B
H or L
input
H
L
H or L
L
L
C
L
H
input
input
L
H
H or L
D
L
L
L
H
input
input
input
Fig. 5.
3-state buffer function
7.3. 3-state inverter functions available
Table 7. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care. See
Fig. 6.
Function
3-state inverter
Input
OE
L
L
L
L
L
L
L
A
input
X
L
H
H
H or L
H
OE
input
Y
001aah327
B
H or L
input
H
L
H or L
H
H
C
L
H
input
input
L
H
H or L
D
H
H
H
L
input
input
input
Fig. 6.
3-state inverter function
74LVC1G99
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 10.1 — 22 October 2018
5 / 26
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