f = 80.000001 MHz, all Vdds. For other freq, T_oe = 100 ns + 3
clock periods
See Figure 8 for resume timing diagram
f = 156.25 MHz, Vdd = 2.5V, 2.8V or 3.3V
f = 156.25 MHz, Vdd = 1.8V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz
LVCMOS Output Characteristics
Output Low Voltage
VOL
–
–
10%
Vdd
Input Characteristics
Input Pull-up Impedance
Input Capacitance
Startup Time
OE Enable/Disable Time
Resume Time
RMS Period Jitter
RMS Phase Jitter (random)
Z_in
C_in
T_start
T_oe
T_resume
T_jitt
T_phj
–
–
–
–
–
–
–
–
100
5
–
–
7
1.5
2
0.5
250
–
10
115
10
Jitter
2
3
1
ps
ps
ps
kΩ
pF
ms
ns
ms
Startup and Resume Timing
Notes:
1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.
2. The typical value of any parameter in the Electrical Characteristics table is specified for the nominal value of the highest voltage option for that parameter and at
25°C temperature.
3. All max and min specifications are guaranteed across rated voltage variations and operating temperature ranges, unless specified otherwise
4. Initial tolerance is measured at Vin = Vdd/2
5. Absolute Pull Range (APR) is defined as the guaranteed pull range over temperature and voltage.
6. APR = pull range (PR) - frequency stability (F_stab) - Aging (F_aging)
Rev. 1.01
Page 2 of 9
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SiT3809
80 MHz to 220 MHz MEMS VCXO
The Smart Timing Choice
The Smart Timing Choice
Table 2. Pin Description. 4-Pin Configuration
(For 2.5 x 2.0 mm and 3.2 x 2.5 mm packages)
Pin
1
2
3
4
Symbol
VIN
GND
CLK
VDD
Input
Power
Power
Input
Power
Electrical ground
Power supply voltage
Oscillator output power
[7]
GND
2
3
Top View
Functionality
VIN
1
4
0-Vdd: produces voltage dependent frequency change
VDD
CLK
Note:
7. A capacitor value of 0.1 µF between VDD and GND is recommended.
Figure 1.
Table 3. Pin Description. 6-Pin Configuration
(For 5.0 x 3.2 mm and 7.0 x 5.0 mm packages)
Pin
1
Symbol
VIN
Input
No
Connect
2
NC/OE/ ST
Output
Enable
Standby
3
4
5
6
GND
CLK
NC
VDD
Power
Output
No
Connect
Power
Functionality
0-Vdd: produces voltage dependent frequency change
H or L or Open: No effect on output frequency or other device
functions
H or Open
[8]
: specified frequency output
L: output is high
H or Open
[8]
: specified frequency output
L: output is low (weak pull down)
[9]
. Oscillation stops
Electrical ground
Oscillator output
H or L or Open: No effect on output frequency or other device
functions
Power supply voltage
[10]
VIN
NC/OE/ST
GND
1
6
Top View
VDD
NC
CLK
2
5
3
4
Figure 2.
Notes:
8. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 2 in the 6-pin package is not externally driven. If pin 2 needs to be left floating, use
the NC option
9. Typical value of the weak pull-down impedance is 5 mΩ
10. A capacitor value of 0.1 µF between VDD and GND is recommended.
Table 4. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of
the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
VDD
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Min.
-65
-0.5
–
–
Max.
150
4
2000
260
Unit
°C
V
V
°C
Table 5. Thermal Consideration
Parameter
7050
5032
3225
2520
JA, 4 Layer Board
(°C/W)
191
97
109
117
JA, 2 Layer Board
(°C/W)
263
199
212
222
JC, Bottom
(°C/W)
30
24
27
26
Table 6. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.01
Page 3 of 9
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SiT3809
80 MHz to 220 MHz MEMS VCXO
The Smart Timing Choice
The Smart Timing Choice
Phase Noise Plot
SiT3809, 100MHz, Pull range ±100ppm, 3.3V, LVCMOS output
-80
-90
Phase Noise (dBc/Hz)
-100
-110
-120
-130
-140
-150
-160
3
10
Integrated Random Phase Jitter (RMS, 12kHz - 20MHz): 0.51 ps
10
4
10
5
10
6
10
7
Offset Frequency (Hz)
Figure 3. Phase Noise
Test Circuit and Waveform
Vdd
Vout
Test
Point
6
15pF
(including probe
and fixture
capacitance)
Power
Supply
0.1µF
5
Vout
Test
Point
4
Power
Supply
0.1µF
3
4
15pF
(including probe
and fixture
capacitance)
1
2
1
2
3
OE/ST Function
Vc
OE/ST Function
Vc
Vdd
Figure 4. Test Circuit (4-Pin Device)
Figure 5. Test Circuit (6-Pin Device)
tr
90% Vdd
50%
10% Vdd
High Pulse
(TH)
Period
tf
Low Pulse
(TL)
Figure 6. Waveform
Notes:
11. Duty Cycle is computed as Duty Cycle = TH/Period.
12. SiT3809 supports the configurable duty cycle feature. For custom duty cycle at any given frequency, contact
SiTime.
Rev. 1.01
Page 4 of 9
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SiT3809
80 MHz to 220 MHz MEMS VCXO
The Smart Timing Choice
The Smart Timing Choice
Timing Diagram
Vdd
50% Vdd
Pin 4 Voltage
T_start
No Glitch
during start up
80% Vdd, 2.5/2.8/3.3V devices
80% Vdd, 1.8V devices
Vdd
ST Voltage
T_resume
CLK Output
CLK Output
T_start: Time to start from power-off
T_resume: Time to resume from ST
Figure 7. Startup Timing (OE/ST Mode)
u
Vdd
50% Vdd
OE Voltage
T_oe
Figure 8. Standby Resume Timing (ST Mode Only)
Vdd
OE Voltage
50% Vdd
T_oe
CLK Output
CLK Output
HZ
T_oe: Time to re-enable the clock output
T_oe: Time to put the output in High Z mode
Figure 9. OE Enable Timing (OE Mode Only)
Figure 10. OE Disable Timing (OE Mode Only)
Notes:
13. SiT3809 supports “no runt” pulses and “no glitch” output during startup or resume.
14. SiT3809 supports gated output which is accurate within rated frequency stability from the first cycle.
FPGA/CPLD
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