S i 5 3 0 / 5 31
P
R E L I M I N A R Y
D
A TA
S
H E E T
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 6.
Applications
SONET/SDH
Networking
SD/HD video
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 5.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK+
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Preliminary Rev. 0.4 5/06
Copyright © 2006 by Silicon Laboratories
Si530/531
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si530/531
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
1
Symbol
V
DD
Test Condition
3.3 V option
2.5 V option
1.8 V option
Supply Current
I
DD
Output enabled
TriState mode
Output Enable (OE)
2
V
IH
V
IL
Operating Temperature Range
T
A
Min
2.97
2.25
1.71
—
—
0.75 x V
DD
—
–40
Typ
3.3
2.5
1.8
90
60
—
—
—
Max
3.63
2.75
1.89
—
—
—
0.5
85
mA
V
Units
V
ºC
Notes:
1.
Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 6 for further details.
2.
OE pin includes a 17 kΩ pullup resistor to V
DD
. Pulling OE to ground causes outputs to tristate.
Table 2. CLK± Output Frequency Characteristics
Parameter
Nominal Frequency
1,2
Symbol
f
O
Test Condition
LVPECL/LVDS/CML
CMOS
Min
10
10
—
–20
–50
Typ
—
—
±1.5
—
—
—
—
Max
945
160
—
+20
+50
±10
10
Units
MHz
Initial Accuracy
f
i
Measured at +25 °C at
time of shipping
ppm
ppm
ppm
ms
Temperature Stability
1,3
Aging
Powerup Time
4
∆f/f
O
Frequency drift over
projected 15 year life
f
a
t
OSC
—
—
Notes:
1.
See Section 3. "Ordering Information" on page 6 for further details.
2.
Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3.
Selectable parameter specified by part number.
4.
Time from powerup or tristate mode to f
O
.
2
Preliminary Rev. 0.4
Si530/531
Table 3. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option
1
Symbol
V
O
V
OD
V
SE
Test Condition
mid-level
swing (diff)
swing (single-ended)
mid-level
swing (diff)
Min
V
DD
– 1.42
1.1
0.5
1.125
0.32
Typ
—
Max
V
DD
– 1.25
1.9
0.93
1.275
0.50
Units
V
V
PP
V
PP
V
V
PP
—
—
1.20
0.40
LVDS Output Option
2
V
O
V
OD
CML Output Option
2
V
O
V
OD
mid-level
swing
(diff)
I
OH
= 32 mA
I
OL
= 32 mA
—
0.70
0.8 x V
DD
V
DD
– 0.75
0.95
—
—
—
1
—
—
1.20
V
DD
V
V
PP
V
CMOS Output Option
3
V
OH
V
OL
—
—
—
45
0.4
350
—
55
Rise/Fall time (20/80%)
t
R,
t
F
LVPECL/LVDS/CML
CMOS with CL = 15 pF
ps
ns
%
Symmetry (duty cycle)
SYM
LVPECL:
LVDS:
CMOS:
V
DD
– 1.3 V (diff)
1.25 V (diff)
V
DD
/2
Notes:
1.
50
Ω
to V
DD
– 2.0 V.
2.
R
term
= 100
Ω
(differential).
3.
C
L
= 15 pF
Table 4. CLK± Output Phase Jitter
Parameter
Phase Jitter (RMS)*
for F
OUT
> 500 MHz
Phase Jitter (RMS)*
for F
OUT
of 125 to 500 MHz
Symbol
Test Condition
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
12 kHz to 20 MHz (OC-48)
Min
—
—
—
Typ
0.27
0.30
0.50
Max
—
—
—
Units
ps
ps
φ
J
φ
J
*Note:
Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.
Table 5. CLK± Output Period Jitter
Parameter
Period Jitter*
for F
OUT
< 160 MHz
Symbol
J
PER
Test Condition
RMS
Peak-to-Peak
Min
—
—
Typ
1
5
Max
—
—
Units
ps
*Note:
Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.
Preliminary Rev. 0.4
3
Si530/531
Table 6. Absolute Maximum Ratings
1
Parameter
Supply Voltage
Input Voltage (any input pin)
Storage Temperature
ESD Sensitivity (HBM, per JESD22-A114)
Soldering Temperature (Pb-free profile)
2
Soldering Temperature Time @ T
PEAK
(Pb-free profile)
2
Symbol
V
DD
V
I
T
S
ESD
T
PEAK
t
P
Rating
–0.5 to +3.8
–0.5 to V
DD
+ 0.3
–55 to +125
>2500
260
10
Units
Volts
Volts
ºC
Volts
ºC
seconds
Notes:
1.
Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions.
2.
Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO
for further information, including
soldering profiles.
Table 7. Environmental Compliance
The Si530/531 meets the following qualification test requirements.
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross & Fine Leak
Resistance to Solvents
Conditions/ Test Method
MIL-STD-883F, Method 2002.3 B
MIL-STD-883F, Method 2007.3 A
MIL-STD-883F, Method 203.8
MIL-STD-883F, Method 1014.7
MIL-STD-883F, Method 2016
4
Preliminary Rev. 0.4
Si530/531
2. Pin Descriptions
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
OE
NC
GND
1
2
3
6
5
4
V
DD
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
NC
CLK+
CLK–
CLK+
Si530
LVDS/LVPECL/CML
Si530
CMOS
Si531
LVDS/LVPECL/CML
Table 8. Pinout for Si530 Series
Pin
1
Symbol
OE (CMOS only)
OE
(LVPECL,LVDS,
CML)
GND
CLK+
CLK–
V
DD
LVDS/LVPECL/CML Function
No connection
Output enable
0 = clock output disabled (outputs tristated)
1 = clock output enabled
Electrical and Case Ground
Oscillator Output
Complementary output
Power Supply Voltage
CMOS Function
Output enable
0 = clock output disabled (outputs tristated)
1 = clock output enabled
No connection
Electrical and Case Ground
Oscillator Output
No connection
Power Supply Voltage
2
3
4
5
6
Table 9. Pinout for Si531 Series
Pin
1
2
3
4
5
6
Symbol
OE (LVPECL, LVDS, CML)
No connection
GND
CLK+
CLK–
V
DD
LVDS/LVPECL/CML Function
Output enable
0 = clock output disabled (outputs tristated)
1 = clock output enabled
No connection
Electrical and Case Ground
Oscillator Output
Complementary output
Power Supply Voltage
Preliminary Rev. 0.4
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
