74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting
Rev. 03 — 2 August 2007
Product data sheet
1. General description
The 74HC240; 74HCT240 is a high-speed Si-gate CMOS device and is pin compatible
with Low-Power Schottky TTL (LSTTL).
The 74HC240; 74HCT240 is a dual octal inverting buffer/line driver with 3-state outputs.
The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on
nOE causes the outputs to assume a high impedance OFF-state.
The 74HC240; 74HCT240 is similar to the 74HC244; 74HCT244 but has inverting
outputs.
2. Features
s
s
s
s
Inverting 3-state outputs
Multiple package options
Complies with JEDEC standard no. 7 A
ESD protection:
x
HBM JESD22-A114-D exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
s
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC240
74HC240N
74HC240D
74HC240DB
74HC240PW
74HC240BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
DIP20
SO20
SSOP20
TSSOP20
plastic dual in-line package; 20 leads (300 mil)
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT146-1
SOT163-1
SOT339-1
Description
Version
Type number
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
DHVQFN20 plastic dual-in-line compatible thermal enhanced
SOT764-1
very thin quad flat package; no leads; 20 terminals;
body 2.5
×
4.5
×
0.85 mm
DIP20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
74HCT240
74HCT240N
−40 °C
to +125
°C
NXP Semiconductors
74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting
Table 1.
Ordering information
…continued
Package
Temperature range Name
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
Version
SOT163-1
SOT339-1
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SO20
SSOP20
TSSOP20
Type number
74HCT240D
74HCT240DB
74HCT240PW
74HCT240BQ
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
DHVQFN20 plastic dual-in-line compatible thermal enhanced
SOT764-1
very thin quad flat package; no leads; 20 terminals;
body 2.5
×
4.5
×
0.85 mm
4. Functional diagram
2
1A0
1Y0
18
4
1A1
1Y1
16
6
1A2
1Y2
14
1
8
EN
18
16
14
12
15
17
1
1A3
1Y3
12
2
2
17
4
15
6
13
8
11
1
19
1A0
2A0
1A1
2A1
1A2
2A2
1A3
2A3
1OE
2OE
mgu779
1OE
1Y0 18
2Y0 3
1Y1 16
2Y1 5
4
6
8
2A0
2Y0
3
2A1
2Y1
5
19
1Y2 14
2Y2
7
11
1Y3 12
2Y3 9
13
15
17
EN
9
7
5
3
mgu778
13
2A2
2Y2
7
11
2A3
2Y3
9
19
2OE
mgu780
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Functional diagram
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
2 of 18
NXP Semiconductors
74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting
5. Pinning information
5.1 Pinning
74HC240
74HCT240
1OE
2
3
4
5
6
7
8
9
GND 10
2A3 11
GND
(1)
1
terminal 1
index area
20 V
CC
19 2OE
18 1Y0
17 2A0
16 1Y1
15 2A1
14 1Y2
13 2A2
12 1Y3
74HC240
74HCT240
1OE
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
1
2
3
4
5
6
7
8
9
20 V
CC
19 2OE
18 1Y0
17 2A0
16 1Y1
15 2A1
14 1Y2
13 2A2
12 1Y3
11 2A3
001aag233
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
GND 10
001aag234
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
supply pin or input
Fig 4. Pin configuration DIP20, SO20, (T)SSOP20
Fig 5. Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
1OE
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
GND
2A3
1Y3
2A2
1Y2
2A1
1Y1
74HC_HCT240_3
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
output enable input (active LOW)
data input
bus output
data input
bus output
data input
bus output
data input
bus output
ground (0 V)
data input
bus output
data input
bus output
data input
bus output
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
3 of 18
NXP Semiconductors
74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting
Table 2.
Symbol
2A0
1Y0
2OE
V
CC
Pin description
…continued
Pin
17
18
19
20
Description
data input
bus output
output enable input (active LOW)
supply voltage
6. Functional description
Table 3.
Input
nOE
L
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
Function table
[1]
Output
nAn
L
H
X
nYn
H
L
Z
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP20 package
SO20, SSOP20, TSSOP20
and DHVQFN20 packages
[1]
For DIP20 packages: above 70
°C,
P
tot
derates linearly with 12 mW/K.
For SO20 packages: above 70
°C,
P
tot
derates linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60
°C,
P
tot
derates linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60
°C,
P
tot
derates linearly with 4.5 mW/K.
[1]
Conditions
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
−0.5
V < V
O
< V
CC
+ 0.5 V
Min
−0.5
-
-
-
-
−70
−65
-
-
Max
+7
±20
±20
±35
70
-
+150
750
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
mW
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
4 of 18
NXP Semiconductors
74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting
8. Recommended operating conditions
Table 5.
Symbol
74HC240
V
CC
V
I
V
O
∆t/∆V
supply voltage
input voltage
output voltage
input transition rise and fall rate V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
T
amb
74HCT240
V
CC
V
I
V
O
∆t/∆V
T
amb
supply voltage
input voltage
output voltage
input transition rise and fall rate V
CC
= 4.5 V
ambient temperature
4.5
0
0
-
−40
5.0
-
-
1.67
-
5.5
V
CC
V
CC
139
+125
V
V
V
ns/V
°C
ambient temperature
2.0
0
0
-
-
-
−40
5.0
-
-
-
1.67
-
-
6.0
V
CC
V
CC
625
139
83
+125
V
V
V
ns/V
ns/V
ns/V
°C
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC240
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
V
I
= V
IH
or V
IL
output voltage
I
O
=
−20 µA;
V
CC
= 2.0 V
I
O
=
−20 µA;
V
CC
= 4.5 V
I
O
=
−20 µA;
V
CC
= 6.0 V
I
O
=
−6.0
mA; V
CC
= 4.5 V
I
O
=
−7.8
mA; V
CC
= 6.0 V
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
1.2
2.4
3.2
0.8
2.1
2.8
2.0
4.5
6.0
-
-
-
0.5
1.35
1.8
-
-
-
-
-
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
0.5
1.35
1.8
-
-
-
-
-
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
0.5
1.35
1.8
-
-
-
-
-
V
V
V
V
V
V
V
V
V
V
V
Conditions
Min
25
°C
Typ
Max
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
Max
Min
Max
3.98 4.32
5.48 5.81
74HC_HCT240_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 2 August 2007
5 of 18
Microchip MCU
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