74HC74
Dual D Flip−Flop with Set
and Reset
High−Performance Silicon−Gate CMOS
The 74HC74 is identical in pinout to the LS74. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they
are compatible with LSTTL outputs.
This device consists of two D flip−flops with individual Set, Reset,
and Clock inputs. Information at a D−input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip−flop. The Set
and Reset inputs are asynchronous.
Features
14
1
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MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
1
HC74G
AWLYWW
•
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7A Requirements
ESD Performance: HBM
>
2000 V; Machine Model
>
200 V
Chip Complexity: 128 FETs or 32 Equivalent Gates
Pb−Free Packages are Available
14
14
1
TSSOP−14
DT SUFFIX
CASE 948G
1
HC
74
ALYW
G
G
HC74
= Device Code
A
= Assembly Location
L, WL
= Wafer Lot
Y
= Year
W, WW = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
February, 2007
−
Rev. 0
1
Publication Order Number:
74HC74/D
74HC74
PIN ASSIGNMENT
RESET 1
DATA 1
CLOCK 1
SET 1
Q1
Q1
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
RESET 2
DATA 2
CLOCK 2
SET 2
Q2
Q2
RESET 2
DATA 2
CLOCK 2
SET 2
RESET 1
DATA 1
CLOCK 1
SET 1
LOGIC DIAGRAM
1
2
3
4
13
12
11
10
PIN 14 = V
CC
PIN 7 = GND
9
8
Q2
Q2
5
6
Q1
Q1
FUNCTION TABLE
Inputs
Set Reset Clock Data
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
H
L
X
X
X
Outputs
Q
Q
H
L
L
H
H*
H*
H
L
L
H
No Change
No Change
No Change
L
H
*Both outputs will remain high as long as Set and Reset are low, but the output
states are unpredictable if Set and Reset go high simultaneously.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
V
CC
V
in
I
in
I
out
I
CC
P
D
T
stg
T
L
V
out
Parameter
Value
Unit
V
V
V
mA
mA
mA
mW
_C
_C
260
300
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or TSSOP Package)
SOIC Package†
TSSOP Package†
DC Output Voltage (Referenced to GND)
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
– 0.5 to V
CC
+ 0.5
±20
±25
±50
500
450
– 65 to + 150
MAXIMUM RATINGS
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package:
−
6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figures 1, 2, 3)
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Min
2.0
0
– 55
0
0
0
0
Max
6.0
V
CC
+ 125
1000
600
500
400
Unit
V
V
_C
ns
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2
74HC74
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
Parameter
Minimum High−Level Input
Voltage
Test Conditions
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
CC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
2.4 mA
|I
out
|
v
4.0 mA
|I
out
|
v
5.2 mA
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
2.4 mA
|I
out
|
v
4.0 mA
|I
out
|
v
5.2 mA
3.0
4.5
6.0
6.0
6.0
– 55 to
25_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±0.1
2.0
v
85_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±1.0
20
v
125_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.2
3.7
5.2
0.1
0.1
0.1
0.4
0.4
0.4
±1.0
80
mA
mA
V
Unit
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
V
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
I
in
I
CC
Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Guaranteed Limit
Symbol
f
max
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
V
CC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
—
– 55 to
25_C
6.0
15
30
35
100
75
20
17
105
80
21
18
75
30
15
13
10
v
85_C
4.8
10
24
28
125
90
25
21
130
95
26
22
95
40
19
16
10
v
125_C
4.0
8.0
20
24
150
120
30
26
160
130
32
27
110
55
22
19
10
Unit
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
ns
C
in
Maximum Input Capacitance
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Flip−Flop)*
2
f + I
CC
32
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
V
CC
. For load considerations, see Chapter 2 of the
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3
74HC74
TIMING REQUIREMENTS
(Input t
r
= t
f
= 6.0 ns)
Guaranteed Limit
Symbol
t
su
Parameter
Minimum Setup Time, Data to Clock
(Figure 3)
V
CC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
– 55 to
25_C
80
35
16
14
3.0
3.0
3.0
3.0
8.0
8.0
8.0
8.0
60
25
12
10
60
25
12
10
1000
800
500
400
v
85_C
100
45
20
17
3.0
3.0
3.0
3.0
8.0
8.0
8.0
8.0
75
30
15
13
75
30
15
13
1000
800
500
400
v
125_C
120
55
24
20
3.0
3.0
3.0
3.0
8.0
8.0
8.0
8.0
90
40
18
15
90
40
18
15
1000
800
500
400
Unit
ns
t
h
Minimum Hold Time, Clock to Data
(Figure 3)
ns
t
rec
Minimum Recovery Time, Set or Reset Inactive to Clock
(Figure 2)
ns
t
w
Minimum Pulse Width, Clock
(Figure 1)
ns
t
w
Minimum Pulse Width, Set or Reset
(Figure 2)
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figures 1, 2, 3)
ns
ORDERING INFORMATION
Device
74HC74D
74HC74DG
74HC74DR2
74HC74DR2G
74HC74DTR2
74HC74DTR2G
Package
SOIC−14
SOIC−14
(Pb−Free)
SOIC−14
SOIC−14
(Pb−Free)
TSSOP−14*
TSSOP−14*
2500 / Tape & Reel
55 Units / Rail
Shipping
†
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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4
74HC74
SWITCHING WAVEFORMS
t
f
CLOCK
90%
50%
10%
t
w
1/f
max
90%
50%
10%
t
PLH
t
r
t
w
V
CC
GND
SET OR
RESET
Q OR Q
50%
t
PHL
50%
t
PLH
Q OR Q
CLOCK
50%
t
rec
50%
V
CC
GND
t
PHL
Q or Q
t
TLH
t
THL
V
CC
GND
Figure 1.
Figure 2.
VALID
DATA
50%
t
su
50%
t
h
TEST POINT
V
CC
GND
V
CC
GND
*Includes all probe and jig capacitance
DEVICE
UNDER
TEST
OUTPUT
C
L
*
CLOCK
Figure 3.
Figure 4.
SET
4, 10
2, 12
5, 9
Q
DATA
CLOCK
3, 11
6, 8
Q
1, 13
RESET
Figure 5. EXPANDED LOGIC DIAGRAM
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