STL8NH3LL
N-channel 30V - 0.012Ω - 8A - PowerFLAT™
Ultra low gate charge STripFET™ Power MOSFET
General features
Type
STL8NH3LL
■
■
■
■
■
■
V
DSS
30V
R
DS(on)
<0.015Ω
I
D
8A
(1)
Improved die-to-footprint ratio
Very low profile package (1mm max)
Very low thermal resistance
Very low gate charge
Low threshold device
In compliance with the 2002/95/EC Europen
directive
PowerFLAT™(3.3x3.3)
(Chip Scale Package)
Description
This application specific Power MOSFET is the
latest generation of STMicroelectronics unique
“STripFET™” technology. The resulting transistor
is optimized for low on-resistance and minimal
gate charge. The Chip-scaled PowerFLAT™
package allows a significant board space saving,
still boosting the performance.
Internal schematic diagram
Applications
■
Switching application
TOP VIEW
Order codes
Sales Type
STL8NH3LL
Marking
8NH3L
Package
PowerFLAT™ (3.3 x 3.3)
Packaging
Tape & reel
March 2006
Rev 7
1/12
www.st.com
12
Contents:
STL8NH3LL
Contents:
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................ 6
3
4
5
Test circuit
................................................ 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12
STL8NH3LL
Electrical ratings
1
Electrical ratings
Table 1.
Symbol
V
DS
V
GS
I
D(1)
I
D (1)
I
DM(2)
P
TOT(3)
P
TOT(1)
Absolute maximum ratings
Parameter
Drain-Source Voltage (V
GS
= 0)
Gate-Source Voltage
Drain Current (continuous) at T
C
= 25°C
Drain Current (continuous) at T
C
=100°C
Drain Current (pulsed)
Total Dissipation at T
C
= 25°C
Total Dissipation at T
C
= 25°C
Derating Factor
Value
30
± 18
8
5
32
50
2
0.4
-55 to 150
Unit
V
V
A
A
A
W
W
W/°C
°C
T
J
T
stg
Operating Junction Temperature
Storage Temperature
1. The value is rated according Rthj-pcb
2. Pulse width limited by safe operating area.
3. The vaule is rated according Rthj-c
Table 2.
Symbol
R
thj-case
R
thj-pcb (1)
R
thj-pcb (2)
Thermal resistance
Parameter
Thermal resistance junction-case (Drain)
Thermal resistance junction-pcb
Thermal resistance junction-pcb
Value
2.5
42.8
63.5
Unit
°C/W
°C/W
°C/W
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10sec
2. Steady state
3/12
Electrical characteristics
STL8NH3LL
2
Electrical characteristics
(T
CASE
=25°C unless otherwise specified)
Table 3.
Symbol
V
(BR)DSS
I
DSS
On/off states
Parameter
Drain-Source Breakdown
Voltage
Zero Gate Voltage Drain
Current (V
GS
= 0)
Test Condictions
I
D
= 250µA, V
GS
= 0
V
DS
= Max Rating,
V
DS
= MaxRating @125°C
Min.
30
1
10
±
100
Typ.
Max.
Unit
V
µA
µA
nA
V
Ω
Ω
I
GSS
V
GS(th)
R
DS(on)
Gate Body Leakage Current
V
GS
= ±18V
(V
DS
= 0)
Gate Threshold Voltage
Static Drain-Source On
Resistance
V
DS
= V
GS
, I
D
= 250µA
V
GS
= 10V, I
D
= 4A
V
GS
= 4.5V, I
D
= 4A
1
0.012
0.0135
2.5
0.015
0.017
Table 4.
Symbol
g
fs (1)
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
R
G
Dynamic
Parameter
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Test Condictions
V
DS
=15V, I
D
= 4A
Min.
Typ.
30
965
285
38
9
3.7
3
12
Max.
Unit
S
pF
pF
pF
nC
nC
nC
Ω
V
DS
=25V, f=1 MHz, V
GS
=0
V
DD
=15V, I
D
= 8A
V
GS
=4.5V
(see Figure 7)
f=1 MHz Gate DC Bias = 0
Test Signal Level = 20mV
Open Drain
Gate Input Resistance
0.5
1.5
2.5
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
4/12
STL8NH3LL
Electrical characteristics
Table 5.
Symbol
t
d(on)
t
r
t
d(off)
t
f
Switching times
Parameter
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Test Condictions
V
DD
=15V, I
D
= 4A,
R
G
=4.7Ω, V
GS
=4.5V
(see Figure 13)
Min.
Typ.
15
32
18
8.5
Max.
Unit
ns
ns
ns
ns
Table 6.
Symbol
I
SD
I
SDM(1)
V
SD(2)
t
rr
Q
rr
I
RRM
Source drain diode
Parameter
Source-drain Current
Source-drain Current (pulsed)
Forward on Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
=8A, V
GS
=0
I
SD
=8A,
di/dt = 100A/µs,
V
DD
=20V, Tj=150°C
(see Figure 15)
24
17.4
1.45
Test Condictions
Min
Typ.
Max
8
32
1.3
Unit
A
A
V
ns
nC
A
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration=300µs, duty cycle 1.5%
5/12
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