IDTQS74FCT153AT/CT
HIGH-SPEED CMOS DUAL 4-INPUT MULTIPLEXER
INDUSTRIAL TEMPERATURE RANGE
HIGH-SPEED CMOS
DUAL 4-INPUT
MULTIPLEXER
FEATURES:
•
•
•
•
•
•
•
•
IDTQS74FCT153AT/CT
DESCRIPTION:
CMOS power levels: <7.5mW static
Undershoot clamp diodes on all inputs
True TTL input and output compatibility
Ground bounce controlled outputs
Reduced output swing of 0 to 3.5V
A and C grades with 4.5ns t
PD
for C
I
OL
= 48mA
Available in SOIC and QSOP packages
The IDTQS74FCT153T is a high-speed CMOS TTL-compatible dual
4-input multiplexer. All inputs have clamp diodes for undershoot noise
suppression. All outputs have ground bounce suppression. Outputs will
not load an active bus when Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
EB
EA
S1
S0
I0A
I1A
I2A
I3A
I0B
I1B
I2B
I3B
YA
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
YB
INDUSTRIAL TEMPERATURE RANGE
1
FEBRUARY 2001
DSC-5230/1
© 2001 Integrated Device Technology, Inc.
IDTQS74FCT153AT/CT
HIGH-SPEED CMOS DUAL 4-INPUT MULTIPLEXER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current Max Current Sink/Pin
Input Diode Current, V
IN
< 0
DC Output Current, V
OUT
< 0
Max
–0.5 to +7
–65 to +150
+120
-20
-50
Unit
V
°C
mA
mA
mA
EA
S
1
I
3A
I
2A
I
1A
I
0A
YA
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
EB
S
0
I
3B
I
2B
I
1B
I
0B
YB
I
OUT
I
IK
I
OK
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
4
8
Max.
—
—
Unit
pF
pF
NOTE:
1. This parameter is measured at characterization but not tested.
SOIC/ QSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
Ixx
S
0
- S
1
EA, EB
YA, YB
I/O
I
I
I
O
Data In
Select
Enable
Data Out
Description
FUNCTION TABLE
(1)
Enable
EA
EB
H
X
X
H
L
L
L
L
L
L
L
L
Inputs
S
1
X
X
L
L
H
H
S
0
X
X
L
H
L
H
Output
YA
YB
L
X
X
L
1
0A
1
0B
1
1A
1
1B
1
2A
1
2B
1
3B
1
3A
Function
Disable A
Disable B
S
1
- 0 = 0
S
1
- 0 = 1
S
1
- 0 = 2
S
1
- 0 = 3
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
2
IDTQS74FCT153AT/CT
HIGH-SPEED CMOS DUAL 4-INPUT MULTIPLEXER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±5%
Symbol
V
IH
V
IL
∆V
T
I
IH
I
IL
I
OS
V
IC
V
OH
V
OL
Parameter
Input HIGH Level
Input LOW Level
Input Hysteresis
Input HIGH Current
Input LOW Current
Short Circuit Current
Input Clamp Voltage
Output HIGH Voltage
Output LOW Voltage
V
CC
= Max., V
OUT
= GND
(2)
V
CC
= Min., I
IN
= –18mA, T
A
= 25°C
(2)
V
CC
= Min.
V
CC
= Min.
I
OH
= –15mA
I
OL
= 48mA
–60
—
2.4
—
—
–0.7
—
—
—
–1.2
—
0.5
mA
V
V
V
Test Conditions
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
TLH
- V
THL
for all inputs
V
CC
= Max.
0
≤
V
IN
≤
V
CC
Min.
2
—
—
—
Typ.
(1)
—
—
0.2
—
Max.
—
0.8
—
±5
Unit
V
V
V
µA
NOTES:
1. Typical values are at V
CC
= 5.0V, +25°C ambient.
2. This parameter is guaranteed but not tested.
POWER SUPPLY CHARACTERISTICS
Symbol
I
CC
Parameter
Quiescent Power Supply Current
Test Conditions
(1)
V
CC
= Max.
freq = 0
0V
≤
V
IN
≤
0.2V or
V
CC
- 0.2V
≤
V
IN
≤
V
CC
∆I
CC
Supply Current per Input TTL Inputs HIGH
V
CC
= Max.
V
IN
= 3.4V
(2)
freq = 0
V
CC
= Max.
Outputs Open and Enabled
One Bit Toggling
50% Duty Cycle
Other inputs at GND or V
CC(3,4)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under DC Electrical Characteristics.
2. Per TTL driven input (V
IN
= 3.4V).
3. For flip-flops, I
CCD
is measured by switching one of the data input pins so that the output changes every clock cycle. This is a measurement of device power consumption
only and does not include power to drive load capacitance or tester capacitance.
4. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Output Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Output Frequency
N
i
= Number of Outputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
Min.
—
Max.
1.5
Unit
mA
—
2
mA
I
CCD
Supply Current per Input per MHz
—
0.25
mA/
MHz
3
IDTQS74FCT153AT/CT
HIGH-SPEED CMOS DUAL 4-INPUT MULTIPLEXER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(1)
74FCT153AT
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Parameter
Propagation Delay
Ixx to Y
Propagation Delay
Sx to Y
Propagation Delay
E
to Y
Min.
1.5
1.5
1.5
Max.
5.2
6.6
5.2
Min.
1.5
1.5
1.5
74FCT153CT
Max.
4.5
5.6
4.8
Unit
ns
ns
ns
NOTE:
1. C
LOAD
= 50pF, R
LOAD
= 500Ω unless otherwise noted.
4
IDTQS74FCT153AT/CT
HIGH-SPEED CMOS DUAL 4-INPUT MULTIPLEXER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V
CC
500
Ω
V
IN
Pulse
G enerator
D.U.T.
50pF
R
T
C
L
500
Ω
V
O UT
7.0V
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
All Other Tests
Switch
Closed
Open
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
FCTL link
Test Circuits for All Outputs
DATA
INPUT
t
SU
TIMING
INPUT
ASYNCHRO NOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRON OUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t
R EM
t
H
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
FCTL link
LOW -HIGH-LOW
PULSE
t
W
HIG H-LOW -HIGH
PULSE
FCTL link
1.5V
1.5V
t
SU
t
H
Pulse Width
Set-Up, Hold, and Release Times
ENABLE
SAM E PHASE
INPUT TRANSITIO N
t
PLH
O UTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITIO N
t
PH L
t
PH L
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
FCTL link
DISABLE
3V
CONTRO L
INPUT
t
PZL
OUTPUT
NO RMALLY
LOW
SW ITCH
CLOSED
t
PZH
OUTPUT
NO RMALLY
HIGH
SW ITCH
OPEN
3.5V
1.5V
0.3V
t
PH Z
0.3V
1.5V
0V
t
PLZ
1.5V
0V
3.5V
V
OL
V
OH
0V
FCTL link
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
5
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