ISD4002 SERIES
SINGLE-CHIP, MULTIPLE-MESSAGES
VOICE RECORD/PLAYBACK DEVICES
120-, 150-, 180-, AND 240-SECOND DURATION
-1-
Publication Release Date: September 2003
Revision 1
ISD4002 SERIES
1. GENERAL DESCRIPTION
The ISD4002 ChipCorder
®
series provides high-quality, 3-volt, single-chip record/playback solutions
for 2- to 4-minute messaging applications ideally for cellular phones and other portable products. The
CMOS-based devices include an on-chip oscillator, anti-aliasing filter, smoothing filter, AutoMute
®
feature, audio amplifier, and high density multilevel Flash memory array. The ISD4002 series is
designed to be used in a microprocessor- or microcontroller-based system. Address and control are
accomplished through a Serial Peripheral Interface (SPI) or Microwire Serial Interface to minimize pin
count.
Recordings are stored into the on-chip Flash memory cells, providing zero-power message storage.
This unique single-chip solution utilizes Winbond’s patented multilevel storage technology. Voice and
audio signals are directly stored onto memory array in their natural form, providing high-quality voice
reproduction.
-2-
ISD4002 SERIES
2. FEATURES
•
•
•
Single-chip voice record/playback solution
Single 3 volt supply
Low-power consumption
Operating current:
-
-
-
I
CC_Play
= 15 mA (typical)
I
CC_Rec
= 25 mA (typical)
I
CC_Standby
= 1 µA (typical)
Standby current:
•
•
•
•
•
•
•
•
•
•
•
•
•
Single-chip durations of 120, 150, 180, and 240 seconds
High-quality, natural voice/audio reproduction
AutoMute feature provides background noise attenuation
No algorithm development required
Micorcontroller SPI or Microwire™ Serial Interface
Fully addressable to handle multiple messages
Non-volatile message storage
100K record cycles (typical)
100-year message retention (typical)
On-chip clock source
Power consumption controlled by SPI or Microwire control register
Available in die form, PDIP, SOIC, and TSOP
Temperature:
-
-
-
-
Commercial (die): 0°C to +50°C
Commercial (packaged units): 0°C to +70°C
Extended: -20°C to +70°C
Industrial: -40°C to +85°C
-3-
Publication Release Date: September 2003
Revision 1
ISD4002 SERIES
3. BLOCK DIAGRAM
Internal Clock
XCLK
Timing
Sampling Clock
ANA IN-
ANA IN+
Amp
5-Pole Active
Antialiasing Filter
Decoders
Analog Transceivers
960K Cell
Nonvolatile
Multilevel Storage
Array
5-Pole Active
Smoothing Filter
AutoMute
TM
Feature
Amp
AUDOUT
Power Conditioning
Device Control
V
CCA
V
SSA
V
SSA
V
SSA
V
SSD
V
CCD
SCLK
SS
MOSI MISO
INT
RAC
AUX IN
-4-
ISD4002 SERIES
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 3
3. BLOCK DIAGRAM .............................................................................................................................. 4
4. TABLE OF CONTENTS ...................................................................................................................... 5
5. PIN CONFIGURATION ....................................................................................................................... 6
6. PIN DESCRIPTION ............................................................................................................................. 7
7. FUNCTIONAL DESCRIPTION.......................................................................................................... 12
7.1. Detailed Description.................................................................................................................... 12
7.2. Serial Peripheral Interface (SPI) Description.............................................................................. 13
7.2.1. OPCODES ........................................................................................................................... 14
7.2.2. SPI Diagrams ....................................................................................................................... 15
7.2.3. SPI Control and Output Registers........................................................................................ 16
8. TIMING DIAGRAMS.......................................................................................................................... 18
9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 20
9.1. Operating Conditions .................................................................................................................. 21
10. ELECTRICAL CHARACTERISTICS ............................................................................................... 22
10.1. Parameters For Packaged Parts
........................................................................................ 22
10.2. Parameters For Die
.............................................................................................................. 25
10.3. SPI AC Parameters
.............................................................................................................. 26
11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 27
12. PACKAGING AND DIE INFORMATION ......................................................................................... 30
12.1. 28-Lead 300-Mil Plastic Small Outline IC (SOIC)..................................................................... 30
12.2. 28-Lead 600-Mil Plastic Dual Inline Package (PDIP) ............................................................... 31
12.3. 28-Lead 8x13.4mm Plastic Thin Small Outline Package (TSOP) Type 1 ................................ 32
12.4. Die Information ......................................................................................................................... 33
13. ORDERING INFORMATION........................................................................................................... 35
14. VERSION HISTORY ....................................................................................................................... 36
-5-
Publication Release Date: September 2003
Revision 1
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
