The ISL88042 is a Quadruple voltage-monitoring supervisor
combining competitive reset threshold accuracy and low
power consumption. This device combines popular functions
such as Power-On Reset, Undervoltage Supply Supervision,
reset signaling and Manual Reset. Monitoring four different
supplies in a 8 Ld 2x3 TDFN package, the ISL88042 devices
can help to lower system cost, reduce board space
requirements, and increase the reliability of multi-voltage
systems.
Low V
DD
detection circuitry protects the user’s system from
low voltage conditions, resetting the system when V
DD
or
any of the other monitored power supply voltages fall below
their respective minimum voltage thresholds. The reset
signal remains asserted until all of these voltages return to
proper operating levels and stabilize.
Two of the four voltage monitors have preset thresholds for
either dual 3.3V or one each for one 5V and one 3.3V
supplies. Users can adjust the threshold voltages of the third
and fourth voltage monitors in order to meet specific system
level requirements.
FN6655
Rev 2.00
July 26, 2010
Features
• Quadruple Voltage Monitoring
• Fixed-Voltage Options Allow Precise Monitoring of +5.0V
and +3.3V Power Supplies
• Two Adjustable Voltage Inputs Monitor Voltages > 0.6V
• 95ms Nominal Reset Pulse Width
• Manual Reset Capability
• Reset Signals Valid Down to V
DD
= 1V
• Immune to Power-Supply Transients
• Low 22µA Maximum Supply Current at 5V
• Pb-Free (RoHS Compliant)
Applications
• Telecom and Datacom Systems
• Routers and Servers
• Access Concentrators
• Cable/Satellite Applications
Pinout
ISL88042
(8 LD TDFN)
TOP VIEW
MR
V
DD
V2MON
GND
1
2
3
4
EPAD
8
7
6
5
RST
V
DDA
V4MON
V3MON
• Desktop and Notebook Computer Systems
• Data Storage Equipment
• Set-Top Boxes
• Industrial Equipment
• Multi-Voltage Systems
(GND)
Ordering Information
PART NUMBER
(Notes 1, 2)
ISL88042IRTHFZ-T
ISL88042IRTHFZ-TK
ISL88042IRTEEZ-T
ISL88042IRTEEZ-TK
ISL88042IRTJJZ-T
ISL88042IRTJJZ-TK
NOTES:
1.
Please refer to TB347 for details on reel specifications
.
2.
These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020
.
PART
MARKING
4P6
4P6
2P9
2P9
2P8
2P8
V
TH1
(V)
4.60
4.60
2.87
2.87
2.78
2.78
V
TH2
(V)
3.09
3.09
2.95
2.95
2.86
2.86
TEMP RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
Tape & Reel
(Pb-free)
8 Ld TDFN
8 Ld TDFN
8 Ld TDFN
8 Ld TDFN
8 Ld TDFN
8 Ld TDFN
PKG.
DWG. #
L8.2x3A
L8.2x3A
L8.2x3A
L8.2x3A
L8.2x3A
L8.2x3A
FN6655 Rev 2.00
July 26, 2010
Page 1 of 8
ISL88042
Pin Descriptions
ISL88042
PIN NUMBER
1
2
3
4
5
6
7
8
PIN NAME
MR
V
DD
V2MON
GND
V3MON
V4MON
V
DDA
RST
FUNCTION
Active-Low open drain manual reset input with internal pull-up resistor
Chip Bias Input and primary integrated preset undervoltage monitor
Operating Temperature Range (Industrial) . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
3.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
SYMBOL
V
DD
I
DD1
I
DD2
I
DDA
Over the recommended operating conditions, unless otherwise specified.
TEST CONDITIONS
MIN
(Note 5)
2.0
V
DD
= 5.0V
V2MON = 3.3V
V3MON, V4MON = 1.0V
14
5.5
19
TYP
MAX
(Note 5)
5.5
22
8
100
UNITS
V
µA
µA
nA
PARAMETER
Supply Voltage Range
V
DD
Supply Current
V2MON Input Current
V3MON, V4MON Input Current
VOLTAGE THRESHOLDS
V
TH1
Fixed Voltage Trip Point for V
DD
ISL88042IRTHFZ
ISL88042IRTEEZ
ISL88042IRTJJZ
V
TH1HYST
Hysteresis of V
TH1
V
TH1
= 4.60V
V
TH1
= 2.87V
V
TH1
= 2.78V
V
TH2
Fixed Voltage Trip Point for V2MON
ISL88042IRTHFZ
ISL88042IRTEEZ
ISL88042IRTJJZ
V
TH2HYST
Hysteresis of V
TH2
V
TH2
= 3.09V
V
TH2
= 2.96V
V
TH2
= 2.86V
V
REF
V
REF
V
REFHYST
RESET
V
OL
Reset Output Voltage Low
V
DD
3.3V, Sinking 2.5mA
V
DD
< 3.3V, Sinking 1.5mA
t
RPD
t
POR
V
TH
to Reset Asserted Delay
POR Timeout Delay
V3MON, V4MON < 3V
40
0.05
0.05
6
95
150
0.40
0.40
V
V
µs
ms
ISL88042IRTHFZ, ISL88042IRTEEZ
Adj. Reset Threshold Voltage
V
TH
for V3MON, V4MON
0.572
0.554
2.936
2.815
2.725
4.370
2.734
2.647
4.600
2.872
2.780
92
58
58
3.090
2.957
2.860
61
60
60
0.600
0.581
12
0.630
0.610
V
V
mV
3.245
3.099
3.000
4.830
3.010
2.914
V
V
V
mV
mV
mV
V
V
V
mV
mV
ISL88042IRTJJZ Adj. Reset Threshold Voltage V
TH
for V3MON, V4MON
Hysteresis Voltage
FN6655 Rev 2.00
July 26, 2010
Page 3 of 8
ISL88042
Electrical Specifications
SYMBOL
MANUAL RESET
V
MRL
V
MRH
t
MR
R
PU
NOTE:
5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
MR Input Voltage Low
MR Input Voltage High
MR Minimum Pulse Width
Internal Pull-Up Resistor
V
DD
- 0.6
550
10
0.8
V
V
ns
k
Over the recommended operating conditions, unless otherwise specified.
(Continued)
TEST CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNITS
PARAMETER
Pin Descriptions
RST
The RST output is an open drain output, which is asserted
low whenever the following occurs:
1. The device is initially powered up to 1V or
2. V
DD
, V2MON, V3MON or V4MON fall below their
minimum voltage sense level.
.
V
DD
V2MON
RST
MR
ISL88042
V3MON
PB
RESET
SIGNAL
MR
The MR input is an active low debounced input to which a
user can connect a push-button to add manual reset
capability or use a signal to pull low. MR has an internal
pull-up resistor.
V4MON
GND
FIGURE 1. TYPICAL APPLICATION DIAGRAM
V
DD
The V
DD
pin is the IC power supply terminal. The voltage at
this pin is compared against an internal factory-programmed
voltage trip point, V
TH1
. RST is first asserted low when the
device is initially powered and V
DD
< 1V and then at any
time thereafter when V
DD
falls below V
TH1
. The device is
designed with hysteresis to help prevent chattering due to
noise and is immune to brief power-supply transients.
Principles of Operation
The ISL88042 device provides those functions needed for
monitoring critical voltages, such as power-supply and battery
functions in microprocessor systems. It provides such features
as Power-On Reset control, supply voltage supervision, and
Manual Reset Assertion. The integration of all these features
along with competitive reset threshold accuracy and low power
consumption, makes the ISL88042 device suitable for a wide
variety of applications needing multi-voltage monitoring. See
Figure 1 for the “Typical Application Diagram”.
V2MON
The V2MON input is the second preset monitored voltage
that causes the RST output to go low when the voltage on
V2MON falls below V
TH2
.
Low Voltage Monitoring
During normal operation, the ISL88042 monitors the voltage
levels of V
DD
, V2MON, V3MON and V4MON. If the voltage on
any of these four inputs falls below their respective voltage trip
points, a reset is asserted (RST = low) to prevent the
microprocessor from operating during a power failure or
brownout condition. This reset signal remains low until the
voltages exceeds the voltage threshold settings for the reset
time delay period t
POR
.
The ISL88042 allows users to customize the minimum voltage
sense level for two of the four monitored voltages. For example,
the user can adjust the voltage input trip point (V
TRIP
) for the
V3MON and V4MON inputs. To do this, connect an external
resistor divider network to the VxMON pin in order to set the trip
V3MON, and V4MON
The VxMON inputs provide monitoring and UV compliance
of three additional voltages through resistor dividers. A reset
is issued on the ISL88042 if the voltage on any VxMON falls
below the internal V
REF
of 0.6V.
FN6655 Rev 2.00
July 26, 2010
Page 4 of 8
ISL88042
point to some other voltage above 600mV according to
Equation 1:
V
TRIP
=
0.6V
R
1
+
R
2
/ R
2
(EQ. 1)
The reset signal remains active until V
DD
rises above the
minimum voltage sense level for time period t
POR
. This
ensures that the supply voltage has stabilized to sufficient
operating levels.
Power-On Reset (POR)
Applying power to the ISL88042 activates a POR circuit, which
makes the reset pin(s) active (i.e. RST goes high while RST
goes low). These signals provide several benefits:
• They prevent the system microprocessor from starting to
operate with insufficient voltage.
• They prevent the processor from operating prior to
stabilization of the oscillator.
• They ensure that the monitored device is held out of
operation until internal registers are properly loaded.
• They allow time for an FPGA to download its configuration
prior to initialization of the circuit.
V
TH1/
V
TH2
V
DD /
V2MON
Manual Reset
The manual-reset input (MR) allows the user to trigger a reset
by using a push-button switch or by signaling the input low. The
MR input is an active low debounced input. Reset is asserted if
the MR pin is pulled low to less than 100mV for the minimum
MR pulse width or longer while the push-button is closed. After
MR is released, the reset output remains asserted low for t
POR
(200ms) and then is released.
Figures 2 and 3 illustrate the ISL88042’s operation.
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