BUK9606-40B
N-channel TrenchMOS logic level FET
Rev. 02 — 1 February 2011
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
AEC Q101 compliant
Low conduction losses due to low
on-state resistance
Suitable for logic level gate drive
sources
Suitable for thermally demanding
environments due to 175 °C rating
1.3 Applications
12 V loads
Automotive systems
General purpose power switching
Motors, lamps and solenoids
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
drain-source on-state
resistance
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
V
GS
= 5 V; T
mb
= 25 °C;
see
Figure 1;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
V
GS
= 10 V; I
D
= 25 A;
T
j
= 25 °C
V
GS
= 5 V; I
D
= 25 A;
T
j
= 25 °C; see
Figure 11;
see
Figure 12
[1]
Min
-
-
-
-
-
Typ
-
-
-
4.1
5.7
Max Unit
40
75
203
5
6.4
V
A
W
mΩ
mΩ
Static characteristics
Nexperia
BUK9606-40B
N-channel TrenchMOS logic level FET
Table 1.
Symbol
E
DS(AL)S
Quick reference data
…continued
Parameter
non-repetitive
drain-source avalanche
energy
gate-drain charge
Conditions
I
D
= 75 A; V
sup
≤
40 V;
R
GS
= 50
Ω;
V
GS
= 5 V;
T
j(init)
= 25 °C; unclamped
V
GS
= 5 V; I
D
= 25 A;
V
DS
= 32 V; T
j
= 25 °C;
see
Figure 13
Min
-
Typ
-
Max Unit
494
mJ
Avalanche ruggedness
Dynamic characteristics
Q
GD
-
17
-
nC
[1]
Continuous current is limited by package
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
[1]
source
mounting base; connected to drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
2
1
3
SOT404 (D2PAK)
[1]
It is not possible to make connection to pin 2.
3. Ordering information
Table 3.
Ordering information
Package
Name
BUK9606-40B
D2PAK
Description
Version
plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404
(one lead cropped)
Type number
BUK9606-40B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 02 — 1 February 2011
2 of 14
Nexperia
BUK9606-40B
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T
mb
= 25 °C; V
GS
= 5 V; see
Figure 1;
see
Figure 3
T
mb
= 100 °C; V
GS
= 5 V; see
Figure 1
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
T
mb
= 25 °C
pulsed; t
p
≤
10 µs; T
mb
= 25 °C
I
D
= 75 A; V
sup
≤
40 V; R
GS
= 50
Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped
[2]
[1]
[1]
[2]
[2]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
R
GS
= 20 kΩ
Min
-
-
-15
-
-
-
-
-
-55
-55
-
-
-
-
Max
40
40
15
129
75
75
516
203
175
175
75
129
516
494
Unit
V
V
V
A
A
A
A
W
°C
°C
A
A
A
mJ
T
mb
= 25 °C; pulsed; t
p
≤
10 µs;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
Source-drain diode
Avalanche ruggedness
[1]
[2]
Current is limited by power dissipation chip rating
Continuous current is limited by package
150
I
D
(A)
100
03nm23
120
P
der
(%)
80
03na19
Capped at 75 A due to package
50
40
0
0
50
100
150
200
T
mb
(°C)
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Continuous drain current as a function of
mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
©
BUK9606-40B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 02 — 1 February 2011
3 of 14
Nexperia
BUK9606-40B
N-channel TrenchMOS logic level FET
10
3
I
D
(A)
10
2
03nm21
Limit R
DSon
= V
DS
/ I
D
t
p
= 10
µ
s
100
µ
s
Capped at 75 A due to package
1 ms
DC
10 ms
100 ms
10
1
10
−1
1
10
V
DS
(V)
10
2
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
BUK9606-40B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 02 — 1 February 2011
4 of 14
Nexperia
BUK9606-40B
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Parameter
Conditions
Min
-
-
Typ
-
50
Max
0.74
-
Unit
K/W
K/W
thermal resistance from junction see
Figure 4
to mounting base
thermal resistance from junction minimum footprint ; mounted on a PCB
to ambient
1
Z
th(j-mb)
(K/W)
10
−1
03nm22
δ
= 0.5
0.2
0.1
0.05
0.02
10
−2
P
δ
=
t
p
T
single shot
t
T
t
p
10
−3
10
−6
10
−5
10
−4
10
−3
10
−2
10
−1
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9606-40B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 02 — 1 February 2011
5 of 14
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