74LVC594A-Q100
Rev. 2 — 21 July 2017
8-bit shift register with output register
Product data sheet
1
General description
The 74LVC594A-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a
storage register. Separate clock and reset inputs are provided on both shift and storage
registers.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial Power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the
device when it is powered down.
The shift register has a serial input (DS) and a serial output (Q7S) for cascading
purposes. Data is shifted on the positive-going transitions of the SHCP input. The data in
the shift register is transferred to the storage register on a positive-going transition of the
STCP input. If both clocks are connected together, the shift register is always one clock
pulse ahead of the storage register. A LOW level on one of the two register reset pins
(SHR and STR) clears the corresponding register.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2
Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
–
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
5 V tolerant inputs/outputs for interfacing with 5 V logic
•
Wide supply voltage range from 1.2 V to 3.6 V
•
CMOS low-power consumption
•
Direct interface with TTL levels
•
Balanced propagation delays
•
All inputs have Schmitt-trigger action
•
Complies with JEDEC standard:
–
JESD8-7A (1.65 V to 1.95 V)
–
JESD8-5A (2.3 V to 2.7 V)
–
JESD8-C/JESD36 (2.7 V to 3.6 V)
•
ESD protection:
–
MIL-STD-883, method 3015 exceeds 2000 V
–
HBM JESD22-A114F exceeds 2 000 V
Nexperia
8-bit shift register with output register
74LVC594A-Q100
3
Applications
•
Serial-to-parallel data conversion
•
Remote control holding register
4
Ordering information
Package
Temperature
range
Name
SO16
TSSOP16
Table 1. Ordering information
Type number
Description
plastic small outline package; 16 leads;
body width 3.9 mm
Version
SOT109-1
74LVC594AD-Q100
74LVC594APW-Q100
74LVC594ABQ-Q100
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
SOT763-1
DHVQFN16 plastic dual in-line compatible thermal
enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
5
Functional diagram
SHCP STCP
11
12
9
15
1
2
DS
14
3
4
5
6
7
10
SHR
13
STR
mbc319
Q7S
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
DS
SHCP
SHR
14
11
10
8-STAGE SHIFT REGISTER
9
Q7S
STCP
STR
12
13
8-BIT STORAGE REGISTER
15 1
2
3
4
5
6
7
mbc320
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Figure 1. Logic symbol
Figure 2. Functional diagram
74LVC594A_Q100
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 2 — 21 July 2017
2 / 21
Nexperia
8-bit shift register with output register
74LVC594A-Q100
STAGE 0
DS
D
CP
SHCP
SHR
Q
D
STAGES 1 TO 6
Q
STAGE 7
D
CP
Q
Q7S
FFSH0
R
FFSH7
R
D
CP
STCP
STR
Q
D
CP
Q
FFST0
R
FFST7
R
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
mbc321
Figure 3. Logic diagram
SHCP
DS
STCP
SHR
STR
Q0
Q1
Q6
Q7
Q7S
mbc323
Figure 4. Timing diagram
74LVC594A_Q100
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 2 — 21 July 2017
3 / 21
Nexperia
8-bit shift register with output register
74LVC594A-Q100
6
Pinning information
6.1 Pinning
74LVC594A-Q100
terminal 1
index area
16 V
CC
15 Q0
14 DS
13 STR
12 STCP
11 SHCP
10 SHR
8
GND
Q7S
9
Q1
2
3
4
5
6
7
1
Q2
16 V
CC
15 Q0
14 DS
13 STR
12 STCP
11 SHCP
10 SHR
9
aaa-009697
74LVC594A-Q100
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
1
2
3
4
5
6
7
8
Q3
Q4
Q5
Q6
Q7
Q7S
aaa-009698
Transparent top view
Figure 5. Pin configuration SO16 and TSSOP16
Figure 6. Pin configuration DHVQFN16
6.2 Pin description
Table 2. Pin description
Symbol
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
GND
Q7S
SHR
SHCP
STCP
STR
DS
V
CC
Pin
15, 1, 2, 3, 4, 5, 6, 7
8
9
10
11
12
13
14
16
Description
parallel data output
ground (0 V)
serial data output
shift register reset (active LOW)
shift register clock input
storage register clock input
storage register reset (active LOW)
serial data input
supply voltage
74LVC594A_Q100
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 2 — 21 July 2017
4 / 21
Nexperia
8-bit shift register with output register
74LVC594A-Q100
7
Functional description
[1]
Table 3. Function table
Input
SHCP STCP SHR
X
X
X
↑
X
X
↑
X
L
X
L
H
Output
STR
X
L
H
X
Function
a LOW-state on SHR only affects the shift register
a LOW-state on STR only affects the storage register
empty shift register loaded into storage register
logic HIGH level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S)
DS
X
X
X
H
Q7S
L
NC
L
Q6S
Qn
NC
L
L
NC
X
↑
↑
↑
H
H
H
H
X
X
NC
Q6S
QnS
QnS
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
[1]
H = HIGH voltage state; L = LOW voltage state; ↑ = LOW-to-HIGH transition; X = don’t care; NC = no change.
8
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
I
IK
V
I
I
OK
V
O
supply voltage
input clamping current
input voltage
output clamping current
output voltage
Conditions
V
I
< 0 V
[1]
Min
-0.5
-50
-0.5
-
[1]
[1]
Max
+6.5
-
+6.5
±50
6.5
V
CC
+ 0.5
±50
100
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
°C
mW
V
O
> V
CC
or V
O
< 0 V
3-state
output HIGH or LOW state
-0.5
-0.5
-
-
-100
-65
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
output current
supply current
ground current
storage temperature
total power dissipation
V
O
= 0 V to V
CC
T
amb
= -40 °C to +125 °C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO16 packages: above 70 °C the value of P
tot
derates linearly with 8 mW/K.
For TSSOP16 packages: above 60 °C the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C the value of P
tot
derates linearly with 4.5 mW/K.
74LVC594A_Q100
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 2 — 21 July 2017
5 / 21
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