OBSOLETE PRODUCT
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
DATASHEET
FN9109
Rev 3.00
Dec 1, 2005
ISL6505
Multiple Linear Power Controller with ACPI Control Interface
The ISL6505 complements other power building blocks
(voltage regulators) in ACPI-compliant designs for
microprocessor and computer applications. The IC
integrates three linear controllers/regulators, switching,
monitoring and control functions into a 20-pin wide-body
SOIC or 20-pin QFN (also known as MLF) 5x5 package.
The ISL6505’s operating mode (active or sleep outputs) is
selectable through two digital control pins, S3 and S5.
One linear controller generates the 3.3V
DUAL
/3.3V
SB
voltage plane from the ATX supply’s 5V
SB
output, powering
the south bridge and the PCI slots through an external NPN
pass transistor during sleep states (S3, S4/S5). In active
state (during S0 and S1/S2), the 3.3V
DUAL
/3.3V
SB
linear
regulator uses an external N-channel pass MOSFET to
connect the outputs directly to the 3.3V input supplied by an
ATX power supply, for minimal losses. The
3.3V
DUAL
/3.3V
SB
output is active for as long as the ATX 5V
SB
voltage is applied to the chip.
A controller powers up the 5V
DUAL
plane by switching in the
ATX 5V output through an NMOS transistor in active states,
or by switching in the ATX 5V
SB
through a PMOS (or PNP)
transistor in S3 sleep state. In S4/S5 sleep states, the
ISL6505 5V
DUAL
output is either shut down or stays on,
based on the state of the EN5 pin.
An internal linear regulator supplies the 1.2V for the voltage
identification circuitry (VID) only during active states (S0 and
S1/S2), and uses the 3V3 pin as input source for its internal
pass element.
A linear controller generates V
OUT1
from the
3.3V
DUAL
/3.3V
SB
voltage plane, using an external NFET.
The voltage is user-programmable to values between 1.2V
and 1.5V, using an external resistor divider. The mode is
user-selectable with the LAN pin; a logic high (or open)
selects the 10/100 LAN mode, where V
OUT1
is always on
(S0-S5); a logic low selects the Gigabit Ethernet mode,
where V
OUT1
is only on during active modes (S0-S2).
Features
• Provides four ACPI-Controlled Voltages
- 5V
DUAL
USB/Keyboard/Mouse
- 3.3V
DUAL
/3.3V
SB
PCI/Auxiliary/LAN
- 1.2V
VID
Processor VID Circuitry
- V
OUT1
(1.2V - 1.5V programmable) LAN/Ethernet
• Excellent Output Voltage Regulation
- All Outputs:
2.0%
over temperature (as applicable)
• Small Size; Very Low External Component Count
• Undervoltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
•
Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• ACPI-Compliant Power Regulation for Motherboards
Ordering Information
TEMP.
PART NUMBER RANGE (°C)
ISL6505CB*
ISL6505CR*
ISL6505CRZ*
(Note 1)
ISL6505EVAL1
ISL6505EVAL2
NOTE:
1.
Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
0 to 70
0 to 70
0 to 70
PACKAGE
20 Ld Wide SOIC
20 Ld 5x5 QFN
20 Ld 5x5 QFN
(Pb-free)
PKG.
DWG. #
M20.3
L20.5x5
L20.5x5
Evaluation Board (SOIC)
Evaluation Board (QFN)
Add “-T” suffix for tape and reel.
Pinouts
- See page 6.
FN9109 Rev 3.00
Dec 1, 2005
Page 1 of 18
ISL6505
Absolute Maximum Ratings
Supply Voltage, V
5VSB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
DLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 7.0V
ESD Classification (Human Body Model) . . . . . . . . . . . . . . . . . .2kV
Thermal Information
Thermal Resistance (Typical)
JA
(
o
C/W)
JC
(
o
C/W)
Recommended Operating Conditions
Supply Voltage, V
5VSB
. . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V
Digital Inputs, V
Sx
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +5.5V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0
o
C to 125
o
C
SOIC Package (Note 2) . . . . . . . . . . .
65
N/A
QFN Package (Notes 3, 4) . . . . . . . . .
35
5
Maximum Junction Temperature (Plastic Package) . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply Current
Shutdown Supply Current
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
5VSB
I
5VSB(OFF)
V
SS
= 0.8V
-
-
6
4
-
-
mA
mA
POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS
5VSB Rising POR Threshold
5VSB Falling POR Threshold
5VSB POR Hysteresis
3V3 Rising Threshold
3V3 Falling Threshold
3V3 Hysteresis
5V Rising Threshold
5V Falling Threshold
5V Hysteresis
VID_PG Rising Threshold
VID_PG Hysteresis
VID_CT Charging Current
Soft-Start Current
Soft-Start Shutdown Voltage Threshold
I
VID_CT
I
SS
V
SD
V
VID_CT
= 0V
4.0
3.15
-
2.8
2.65
-
4.25
4.0
-
-
-
-
-
-
4.3
3.4
0.9
2.93
2.78
150
4.4
4.15
250
1.04
50
10
10
-
4.5
3.55
-
3.0
2.9
-
4.5
4.3
-
-
-
-
-
0.8
V
V
V
V
V
mV
V
V
mV
V
mV
A
A
V
LINEAR REGULATOR (V
OUT1
; DR1 and FB1 pins)
V
OUT1
Regulation
V
OUT1
Nominal Voltage Level
V
OUT1
Undervoltage Rising Threshold
V
OUT1
Undervoltage Hysteresis
DR1 Output Drive Current
I
DR1
V
OUT1
V
OUT1
= 1.2V to 1.5V
Based on external resistors
FB1 pin
FB1 pin
V
3V3DL
= 3.3V
-
-
-
-
-
-
1.5
1.2
50
10
2.0
-
-
-
-
%
V
V
mV
mA
FN9109 Rev 3.00
Dec 1, 2005
Page 4 of 18
ISL6505
Electrical Specifications
PARAMETER
1.2V
VID
LINEAR REGULATOR (V
OUT2
)
1V2VID Regulation
1V2VID Nominal Voltage Level
1V2VID Undervoltage Rising Threshold
1V2VID Undervoltage Hysteresis
1V2VID Output Current
I
1V2VID
V
3V3
= 3.3V
V
1V2VID
-
-
-
-
-
-
1.2
0.92
100
-
2.0
-
-
-
180
%
V
V
mV
mA
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3
(Continued)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
3.3V
DUAL
/3.3V
SB
LINEAR REGULATOR (V
OUT3
)
3V3DL Sleep State Regulation
3V3DL Nominal Voltage Level
3V3DL Undervoltage Rising Threshold
3V3DL Undervoltage Hysteresis
3V3DLSB Output Drive Current
5V
DUAL
SWITCH CONTROLLER (V
OUT4
)
5VDL Undervoltage Rising Threshold
5VDL Undervoltage Hysteresis
5VDLSB Output Drive Current
TIMING INTERVALS
Active State Assessment Past Input UV
Thresholds (Note 5)
Active-to-Sleep Control Input Delay
Falling UV Threshold Timeout (All Monitors)
CONTROL I/O (S3, S5, EN5, LAN, FAULT)
High Level Input Threshold
Low Level Input Threshold
Internal Pull-up Current to 5VSB
Internal Pull-up Current to 5VSB
Input Leakage Current to 5VSB
FAULT Current IOH (to 5VSB)
FAULT Current IOL (to GND)
TEMPERATURE MONITOR
Fault-Level Threshold (Note 6)
Shutdown-Level Threshold (Note 6)
NOTES:
5. Guaranteed by Correlation.
6. Guaranteed by Design.
125
-
-
155
-
-
o
C
o
C
-
V
3V3DL
-
-
-
I
3V3DLSB
V
5VSB
= 5V
30
-
3.3
2.62
150
50
2.0
-
-
-
-
%
V
V
mV
mA
-
-
I
5VDLSB
V
5VDLSB
= 4V
,
V
5VSB
= 5V
-20
4.10
120
-
-
-
-40
V
mV
mA
42
-
-
53
200
10
64
-
-
ms
s
s
S3, S5, EN5, LAN
S3, S5, EN5, LAN
S3, S5 to GND
EN5, LAN to GND
EN5, LAN to 5VSB
FAULT = 4.6V, 5VSB = 5V
FAULT = 0.4V, 5VSB = 5V
-
0.8
-
-
-
-
-
-
-
50
10
-
-7.5
0.75
2.2
-
-
-
10
-
-
V
V
A
A
mA
mA
mA
FN9109 Rev 3.00
Dec 1, 2005
Page 5 of 18
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
