USER’S MANUAL
ISL6420EVAL3
Using the ISL6420 PWM Controller Evaluation Board
AN1159
Rev 0.00
Nov 10, 2004
Advanced Single Synchronous Buck
Pulse-Width Modulation (PWM) Controller
The ISL6420 simplifies the work of implementing a complete
control and protection scheme for a high-performance DC-
DC buck converter. Designed to drive N-channel MOSFETs
in a synchronous rectified buck topology, the ISL6420
integrates the control, output adjustment, monitoring and
protection functions into a single package.
The ISL6420 provides simple, single feedback loop, voltage
mode control with fast transient response. The output
voltage of the converter can be precisely regulated to as low
as 0.6V, with a maximum tolerance of ±1.0% over
temperature and line voltage variations.
The operating frequency is fully adjustable from 100kHz to
1.4MHz. High frequency operation offers cost and space
savings.
The error amplifier features a 15MHz gain-bandwidth
product and 6V/µs slew rate that enables high converter
bandwidth for fast transient response. The resulting PWM
duty cycle ranges from 0% to 100%. Selecting the capacitor
value from the ENSS pin to ground sets a fully adjustable
PWM soft-start; while pulling ENSS pin LOW disables the
controller.
The ISL6420 monitors the output voltage and generates a
PGOOD (power good) signal when soft-start is complete and
the output is within regulation. A built-in overvoltage
protection circuit prevents the output voltage from going
above typically 115% of the set point. Protection from
overcurrent conditions is provided by monitoring the r
DS(ON)
of the upper MOSFET to inhibit the PWM operation
appropriately. This approach simplifies the implementation
and improves efficiency by eliminating the need for a current
sensing resistor. The IC also features voltage margining for
networking DC-DC converter applications.
Quick Start Evaluation
The evaluation board is shipped “ready to use” right from the
box. The board has been optimized for a 12V input from a
standard power supply but can accept a range from 4.5V to
16V. The board can be connected to the source and load
with the help of stand-off terminals provided.
Recommended Test Equipment
To test the functionality of the ISL6420, the following
equipment is recommended:
•
•
•
•
An adjustable 12V, 8A capable bench power supply
An electronic load
Four channel oscilloscope with probes
Precision digital multimeter
Power and Load Connections
Refer to the ISL6420EVAL3 schematic for reference
designators.
Jumper Settings
- JP1 controls what terminal post is
connected to the VIN pin of the IC (See the Input Voltage
explanation below). JP2 and JP3, when shorted with a
jumper, pull the GPIO2 and GPIO1 pins to GND. With the
jumpers removed, GPIO2 and GPIO1 will be floating.
Input Voltage -
The ISL6420EVAL3 reference design is
optimized for an input supply of 12V, however, the input
supply can range from 4.5V to 16V.
If using an input supply ranging from 5.6V to 16V, short pins
1 and 2 of jumper JP1. In this mode, the VIN post (P1) is
connected to the drain of the upper MOSFET and the VIN
pin of the IC and the chip is powered by the 5V output
(VCC5, post P5) of the internal LDO.
To use a 5V ±10% input supply, short pins 2 and 3 of JP1
and connect the power supply to the VIN (P1) post and the
VCC5 (P5) post. This will disable the internal LDO and the
chip will be powered by the input power supply.
CAUTION: When JP1 pins 2 & 3 are shorted, applying voltages
>6V can damage the IC.
ISL6420 Reference Design
The ISL6420 evaluation board highlights the operation of the
IC in an embedded application. The evaluation board is
configured for an output voltage of 3.3V and 10A maximum
load.
TABLE 1.
BOARD NAME
ISL6420EVAL3
IC
ISL6420IR
PACKAGE
20 Ld QFN
For quick start evaluation, adjust the power supply to provide
the 12V input voltage and short pins 1 and 2 of JP1. With the
power supply turned off, connect the positive lead of the 12V
supply to the VIN post (P1) and the ground lead to the GND
post (P2).
Output Voltage Loading and Monitoring
- Connect the
positive lead of the electronic load and the positive lead of a
digital multimeter to the VOUT post (P3) and the ground lead
to the GND post (P4). You can use the scope probe terminal
(SC1) to monitor VOUT with an oscilloscope.
AN1159 Rev 0.00
Nov 10, 2004
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ISL6420EVAL3
Start-up
The Power On Reset (POR) function initiates the soft-start
sequence. An internal 10µA current source charges an
external capacitor connected to the ENSS (P9) pin from 0V
to 3.3V. When the ENSS pin reaches 1V the error amplifier
reference voltage ramps from 0V to 0.6V following the slope
of the ENSS pin voltage.
There are two distinct start-up methods for the ISL6420. The
first method is invoked through the application of power to
the IC. The soft-start feature allows for a controlled turn on of
the output once the POR threshold of the input voltage has
been reached. Figure 1 shows the start-up profile of the
regulator in relation to the start-up of the 12V input supply.
FIGURE 2. SHUTDOWN USING ENSS
FIGURE 1. SOFT-START
The second method of start-up is through the use of the
enable feature. Holding the ENSS (P9) pin on the ISL6420
below 1V will disable the regulator by forcing both the upper
and lower MOSFETs off. Releasing the pin allows the
regulator to start-up.
FIGURE 3. POWER DOWN OF THE INPUT SUPPLY
Output Performance
Switching Frequency
The switching frequency of the ISL6420 can be adjusted
from 100kHz to 1.4MHz by connecting a resistor from the RT
pin to GND. The free running frequency of the IC is 300kHz
when the RT pin is tied to VCC5. The evaluation board has a
0 resistor (R9) connecting RT to VCC5. By removing this
0 resistor and placing a resistor (R4) from this pin to GND,
the nominal 300kHz switching frequency can be increased
or decreased as per Figure 4.
Shutdown
As discussed in the previous section, if the ENSS pin is
pulled down and held below 1V the regulator will be turned
off. Figure 2 shows the shutdown profile of the regulator with
the ENSS pin pulled low. Figure 3 shows the shutdown of the
regulator when powering down of the input supply.
AN1159 Rev 0.00
Nov 10, 2004
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ISL6420EVAL3
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
Power Good
PGOOD will be true (open drain) when the FB pin voltage is
within ±10% of the reference voltage and the soft-start
sequence is complete, i.e., once the soft-start capacitor is
finished charging. The status of PGOOD can be monitored
at the PGOOD test point (TP1).
FREQUENCY (kHz)
Overcurrent Protection
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. Figure 7 shows the
overcurrent hiccup mode.
0
25
50
75
RT (k)
100
125
150
FIGURE 4. RT vs SWITCHING FREQUENCY
Output Ripple
Figure 5 shows the ripple voltage on the output of the
regulator at the free running 300kHz frequency and at
600kHz.
The overcurrent function protects the converter from a
shorted output by using the upper MOSFET’s R
DS(ON)
to
monitor the current. This method enhances the converter’s
efficiency and reduces cost by eliminating a current sensing
resistor.
FIGURE 7. OVERCURRENT HICCUP MODE
FIGURE 5. OUTPUT RIPPLE
Efficiency
ISL6420 based regulators enable the design of highly
efficient systems. The efficiency of the evaluation board
using a 12V and a 5V input supply is shown in Figure 6.
98
96
94
EFFICIENCY (%)
92
90
88
86
84
82
80
0
1
2
3
4
5
6
LOAD (A)
7
8
9
10
VIN=12V
VIN=5V
A resistor, R
OCSET
(R8), programs the overcurrent trip level.
The PHASE node voltage is compared to the voltage on the
OCSET pin, while the upper FET is on. A current (100µA
typically) is pulled from the OCSET pin to establish this
voltage across an external resistor. If PHASE is lower than
OCSET, while the upper FET is on, then an overcurrent
condition is detected for that clock cycle. The pulse is
immediately terminated, and a counter is incremented. If an
overcurrent condition is detected for 8 consecutive clock
cycles, and the circuit is not in soft-start, the ISL6420 enters
into hiccup mode. During hiccup, the external capacitor on
the ENSS pin is discharged and soft-start is initiated. During
soft-start, pulse termination limiting is enabled, but the
8-cycle hiccup counter is held in reset until soft-start is
completed.
The overcurrent function will trip at a peak inductor current
(I
PEAK
) determined by,
I
OCSET
R
OCSET
-
I
PEAK
= --------------------------------------------------
R
DS
ON
FIGURE 6. EVALUATION BOARD EFFICIENCY
where I
OCSET
is the internal OCSET current source.
AN1159 Rev 0.00
Nov 10, 2004
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ISL6420EVAL3
The OC trip point varies mainly due to the MOSFET’s
r
DS(ON)
variations. To avoid overcurrent tripping in the
normal operating load range, calculate the R
OCSET
resistor
from the equation above using:
1. The maximum R
DS(ON)
at the highest junction
temperature.
2. The minimum I
OCSET
from the specification table.
Determine
I
PEAK
for I
PEAK
I
OUT
MAX
+
I
2
,
the external feedback resistor (R2) and the external resistor
tied to VMSET (R6).
TABLE 2.
GPIO1
L
L
H
H
GPIO2
L
H
L
H
VOUT
No Change
+ Delta VOUT
- Delta VOUT
Ignored
where
I
is the output inductor ripple current. A small
ceramic capacitor should be placed in parallel with R
OCSET
to smooth the voltage across R
OCSET
in the presence of
switching noise on the input voltage.
The overcurrent trip point on the evaluation board has been
set to 18A. Figure 7 shows the overcurrent hiccup mode.
The evaluation board has a 330k VMSET resistor (R6)
setting a current:
IVM = 2.468V/330k = 7.48µA
and
V(delta) = 7.48µA*20.5k = 0.153V
Figure 8 shows the output voltage in voltage margining
mode for various VMSET resistor values.
3.7
3.6
3.5
3.4
VOUT (V)
3.3
3.2
3.1
3
2.9
2.8
150
175
200
225
250
275
300
325
350
375
400
Transient Performance
Figure 8 shows the response of the output when subjected
to transient loading from 10mA to 10A.
RVMSET (k)
FIGURE 8. TRANSIENT RESPONSE
FIGURE 9. CHANGE IN OUTPUT VOLTAGE FOR VARIOUS
RESISTORS
Voltage Margining
Voltage margining mode is enabled by connecting a
margining set resistor (R6) from the VMSET pin to ground.
This resistor to ground will set a current, which is switched to
the FB pin. The current will be equal to 2.468V divided by the
value of the external resistor tied to the VMSET pin.
The GPIO1 (P8) and GPIO2 (P7) pins control the current
switching as per Table 2 below. The power supply output
increases when GPIO2 is HIGH and decreases when GPIO1
is HIGH. Using a jumper to short the pins of JP2 and JP3 will
pull GPIO1 and GPIO2 LOW. Remove these jumpers to pull
GPIO1 or GPIO2 HIGH for voltage margining. The amount
that the output voltage of the power supply changes with
voltage margining will be equal to 2.468V times the ratio of
The slew time of the current is set by an external capacitor
(C13) on the CDEL pin, which is charged and discharged
with a 100µA current source. The change in voltage on the
capacitor is 2.5V. This same capacitor is also used to set the
PGOOD rise delay. When PGOOD is low, the internal
PGOOD circuitry uses the capacitor and when PGOOD is
high the voltage margining circuit uses the capacitor. The
slew time for voltage margining can be in the range of 300µs
to 2.5ms. The CDEL capacitor on the evaluation board is
0.1µF leading to a voltage margining slew rate of 2.5ms.
AN1159 Rev 0.00
Nov 10, 2004
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ISL6420EVAL3
Figure 8 shows positive and negative voltage margining with
a CDEL capacitor of 0.1µF.
FIGURE 10. VOLTAGE MARGINING SLEW TIME
Conclusion
The ISL6420 is a versatile PWM controller. The small
footprint and the numerous features enables the
implementation of compact and highly efficient regulators,
delivering low voltage power solutions.
References
For Intersil documents available on the web, see
http://www.intersil.com/
[1]
ISL6420 Data Sheet,
Intersil Corporation, File No.
FN9073.
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Nov 10, 2004
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