DATASHEET
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128,
ISL6130
The Intersil ISL6123, ISL6124, ISL6125, ISL6126, ISL6127,
ISL6128 and ISL6130 are integrated 4-channel
controlled-on/controlled-off power-supply sequencers with
supply monitoring, fault protection and a “sequence completed”
signal (RESET). For larger systems, more than four supplies can
be sequenced by simply connecting a wire between the
SYSRESET pins of cascaded ICs. The ISL6125 uses four active
open-drain outputs to control the on/off sequencing of four
supplies. The other sequencers use a patented, micropower 7x
charge pump to drive four external low-cost NFET switch gates
above the supply rail by 5.3V. These ICs can be biased from 5V
down to 1.5V by any supply.
The 4-channel ISL6123 (ENABLE input), ISL6124 (ENABLE
input) and ISL6125 offer the designer 4-rail control when all
four rails must be in minimal compliance before turn-on and
during operation. The ISL6123 and ISL6130 have a low-power
standby mode when disabled, which is suitable for
battery-powered applications.
The ISL6125 operates like the ISL6124, but instead of
charge-pump-driven gate drive outputs, it has open-drain logic
outputs for direct interface to other circuitry.
In contrast, for the ISL6126 and ISL6130, each of the four
channels operates independently. Each GATE turns on once its
individually associated input voltage requirements are met.
The ISL6127 is a pre-programmed A-B-C-D turn-on and D-C-B-A
turn-off sequenced IC. Once all inputs are in compliance and
ENABLE is asserted, sequencing begins. Each subsequent GATE
turns on after the previous one turns on.
The ISL6128 has two groups of two channels, each with its
independent I/O. It is ideal for voltage sequencing into
redundant capability loads. All four inputs must be satisfied
before turn-on, but a single group fault is ignored by the other
group.
External resistors provide flexible voltage threshold
programming of monitored rail voltages. Delay and
sequencing are provided by external capacitors for ramp-up
and ramp-down.
Additional I/O is provided for indicating and driving the RESET
state in various configurations.
For volume applications, other programmable options and
features are available. Contact
Intersil sales support
with your
needs.
FN9005
Rev 1.00
September 26, 2012
Features
• Enables Arbitrary Turn-on and Turn-off Sequencing of Up to Four
Power Supplies (0.7V to 5V)
• Operates From 1.5V to 5V Supply Voltage
• Supplies V
DD
+5.3V of Charge Pumped Gate Drive
• Adjustable Voltage Slew Rate for Each Rail
• Multiple Sequencers Can be Daisy-Chained to Sequence an
Infinite Number of Independent Supplies
• Glitch Immunity
• Undervoltage Lockout for Each Supply
• 1µA Sleep State (ISL6123, ISL6130)
• Active High (ISL6123, ISL6130) ENABLE or Low (ISL6124,
ISL6125, ISL6126, ISL6127, ISL6128) ENABLE Input
• Active Open Drain Version Available (ISL6125)
• Voltage-determined Sequence (ISL6126, ISL6130)
• Pre-programmed Sequence Available (ISL6127)
• Dual Channel Groupings (ISL6128)
• QFN Package
• Pb-free (RoHS-compliant)
Applications
• Graphics Cards
• FPGA/ASIC/Microprocessor/PowerPC Supply Sequencing
• Network Routers
• Telecommunications Systems
V1
V2
V3
V4
V1OUT
V2OUT
V3OUT
V4OUT
GATE D
GATE C
GATE B
UVLO_A
UVLO_B
UVLO_C
UVLO_D
DLY_OFF_A
DLY_OFF_B
DLY_ON_A
DLY_ON_B
DLY_ON_C
V
DD
ENABLE
SYSRST
RESET
GROUND
DLY_OFF_C
DLY_OFF_D
DLY_ON_D
FIGURE 1. TYPICAL ISL6123 APPLICATION
FN9005 Rev 1.00
September 26, 2012
GATE A
Page 1 of 23
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL6123IRZA
ISL6124IRZA
ISL6125IRZA
ISL6126IRZA
ISL6127IRZA
ISL6128IRZA
ISL6130IRZA
ISL6123EVAL1Z
ISL6125EVAL1Z
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130.
For
more information on MSL please see Tech Brief
TB363.
PART MARKING
61 23IRZ
61 24IRZ
61 25IRZ
61 26IRZ
61 27IRZ
61 28IRZ
61 30IRZ
ISL6123 Evaluation Platform
ISL6125 Evaluation Platform
TEMP. RANGE (°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
(Pb-free)
24 Ld 4x4 QFN
24 Ld 4x4 QFN
24 Ld 4x4 QFN
24 Ld 4x4 QFN
24 Ld 4x4 QFN
24 Ld 4x4 QFN
24 Ld 4x4 QFN
PKG. DWG. #
L24.4x4
L24.4x4
L24.4x4
L24.4x4
L24.4x4
L24.4x4
L24.4x4
P1
P2
S3
en
S1
en
V1OUT
V2OUT
V3OUT
V4OUT
VDD
1µA
BIAS
LOCK OUT
VDD+5V
Q-PUMP
S2
en
P3
S4
en
DLY_ONX
1µA
OUT D
OUT C
OUT B
OUT A
V
DD
1.26V
UVLO_A
UVLO_B
UVLO_C
UVLO_D
DLY_OFF_A
DLY_ON_A
SYSRST
1µA
-1µA
ISL6125
RESET
ENABLE
GROUND
DLY_OFFX
DLY_OFF_B
DLY_OFF_C
DLY_OFF_D
DLY_ON_B
DLY_ON_C
DLY_ON_D
10ms
RISING DELAY
1.26V
30µs
FILTER
GATEX
FIGURE 2. ISL6125 APPLICATION
UVLOX
LOGIC
0.633V
EN
SYSRST
150ms
RISING DELAY
RESET
FIGURE 3. ISL6123 BLOCK DIAGRAM (1/4)
FN9005 Rev 1.00
September 26, 2012
Page 2 of 23
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Pin Configurations
ISL6123, ISL6124, ISL6125
(24 LD QFN)
TOP VIEW
DLY_ON_A
UVLO_A
SYSRST
RESET
RESET
ISL6127
(24 LD QFN)
TOP VIEW
UVLO_A
20
SYSRST
VDD
VDD
NC
NC
24
ENABLE_1/
ENABLE_1
GATE_A
*OUTPUT_A
DLY_OFF_C
DLY_OFF_D
GATE_B
*OUTPUT_B
GATE_C
*OUTPUT_C
1
2
3
4
5
6
7
23
22
21
20
19
18 DLY_OFF_A
17 UVLO_C
16 DLY_ON_C
ENABLE_1/
ENABLE_1
GATE_A
NC
NC
GATE_B
GATE_C
1
2
3
4
5
6
24
23
22
21
19
18 NC
17 UVLO_C
16 NC
EPAD
(GND)
15 DLY_ON_D
14 UVLO_D
13 DLY_OFF_B
EPAD
(GND)
NC
15 NC
14 UVLO_D
13 NC
12
UVLO_B
19
18 DLY_OFF_A
17 UVLO_C
16 DLY_ON_C
NC
15 DLY_ON_D
14 UVLO_D
13 DLY_OFF_B
12
UVLO_B
8
9
NC
10
GND
11
NC
12
UVLO_B
7
GATE_D
8
NC
9
NC
10
GND
DLY_ON_A
21
10
GND
11
NC
20
11
ENABLE_2
UVLO_A
*OUTPUT_A, OUTPUT_B, OUTPUT_C, OUTPUT_D ARE UNIQUE TO
ISL6125
GATE_D
*OUTPUT_D
DLY_ON_B
ISL6126, ISL6130
(24 LD QFN)
TOP VIEW
UVLO_A
RESET
ISL6128
(24 LD QFN)
TOP VIEW
RESET
VDD
VDD
23
8
DLY_ON_B
NC
NC
NC
24
ENABLE_1/
ENABLE_1
GATE_A
DLY_OFF_C
DLY_OFF_D
GATE_B
GATE_C
1
2
3
4
5
6
7
GATE_D
23
22
21
20
19
18 DLY_OFF_A
17 UVLO_C
16 NC
ENABLE_1
GATE_A
DLY_OFF_C
DLY_OFF_D
GATE_B
GATE_C
1
2
3
4
5
6
24
EPAD
(GND)
15 NC
14 UVLO_D
13 DLY_OFF_B
8
NC
9
NC
10
GND
11
NC
12
UVLO_B
7
GATE_D
FN9005 Rev 1.00
September 26, 2012
RESET_2
NC
22
9
EPAD
(GND)
Page 3 of 23
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Pin Descriptions
PIN NUMBER
PIN
NAME
V
DD
GND
ENABLE_1/
ENABLE_1
ENABLE_2/
ENABLE_2
RESET
RESET_2
ISL6123, ISL6124,
ISL6125
23
10
1
NC
ISL6126,
ISL6130
23
10
1
NC
ISL6127
23
10
1
NC
ISL6128
23
10
1
11
Bias Return. IC ground.
Input to start on/off sequencing. Input to initiate start of programmed
sequencing of supplies on or off. Enable functionality disabled for 10ms after
UVLO is satisfied. ISL6123 and ISL6130 have ENABLE, and ISL6124,
ISL6125, ISL6126 and ISL6127 have ENABLE. Only ISL6128 has two ENABLE
inputs; one for each 2-channel grouping. ENABLE_1 is for (A, B), and
ENABLE_2 is for (C, D).
RESET Output. RESET provides low signal 150ms after all GATEs are fully
enhanced. Delay is for stabilization of output voltages. RESET asserts low
upon UVLO not being satisfied or ENABLE/ENABLE being deasserted. RESET
outputs are open-drain, N-channel FET and are guaranteed to be in correct
state for VDD down to 1V and are filtered to ignore fast transients on VDD and
UVLO_X.
RESET_2 only exists on ISL6128 for (C, D) group I/O.
Undervoltage Lockout/Monitoring Input. Provides a programmable UV lockout
referenced to an internal 0.633V reference. Filtered to ignore short (<30µs)
transients below programmed UVLO level.
DESCRIPTION
Chip Bias. Bias IC from nominal 1.5V to 5V.
24
NC
24
NC
24
NC
24
9
UVLO_A
UVLO_B
UVLO_C
UVLO_D
DLY_ON_A
DLY_ON_B
DLY_ON_C
DLY_ON_D
DLY_OFF_A
DLY_OFF_B
DLY_OFF_C
DLY_OFF_D
GATE_A
GATE_B
GATE_C
GATE_D
OUTPUT_A
OUTPUT_B
OUTPUT_C
OUTPUT_D
SYSRST
20
12
17
14
21
8
16
15
18
13
3
4
2
5
6
7
2 (ISL6125)
5 (ISL6125)
6 (ISL6125)
7 (ISL6125)
22
20
12
17
14
20
12
17
14
20
12
17
14
21
8
16
15
Gate On Delay Timer Output. Allows programming of delay and sequence for
VOUT turn-on using a capacitor to ground. Each capacitor charged with 1µA
10ms after turn-on initiated by ENABLE/ENABLE. Internal current source
provides delay to associated FET GATE turn-on.
Gate Off Delay Timer Output. Allows programming of delay and sequence for
VOUT turn-off through ENABLE/ENABLE via a capacitor to ground. Each
capacitor charged with 1µA internal current source to an internal reference
voltage, causing corresponding gate to be pulled down, thus turning off FET.
FET Gate Drive Output. Drives external FETs with 1µA current source to soft-
start ramp into load.
18
13
3
4
2
5
6
7
2
5
6
7
18
13
3
4
2
5
6
7
On ISL6125 only, these are ACTIVE open drain outputs that can be pulled up
to a maximum of VDD voltage.
22
System Reset I/O. As an input, allows for immediate and unconditional latch-off
of all GATE outputs when driven low. This input can also be used to initiate
programmed sequence with ‘zero’ wait (no 10ms stabilization delay) from input
signal on this pin being driven high to first GATE. As an output, when there is a UV
condition, this pin pulls low. If common to other SYSRST pins in a multiple IC
configuration, it causes immediate and unconditional latch-off of all other GATEs
on all other ISL612X sequencers.
EPAD
19, 22
Ground. Die Substrate. Can be left floating.
No Connect
GND
NC
EPAD
9, 19
EPAD
EPAD
8, 9, 11, 3, 4, 8, 9,
11, 13,
15, 16,
19, 21, 22 15,16,18,
19, 21
FN9005 Rev 1.00
September 26, 2012
Page 4 of 23
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
ISL612X and ISL6130 Variant Feature Matrix
PART
NAME
ISL6123
CMOS/
TTL
TTL
GATE DRIVE
OR OPEN
DRAIN
OUTPUTS
Gate Drive
REQUIRED
CONDITIONS
FOR INITIAL
START-UP
4 UVLO
1 EN
4 UVLO
1 EN
4 UVLO
1 EN
1 UVLO
1 EN
NUMBER OF
NUMBER OF
UVLO INPUTS CHANNELS THAT
MONITORED TURN OFF WHEN
BY EACH
ONE UVLO
RESET
FAULTS
4 UVLO
4 Gates
PRESET OR
ADJUSTABLE
SEQUENCE
Time Adjustable
On and Off
Time Adjustable
On and Off
Time Adjustable
On and Off
Voltage
Determined ON
Time Adjustable
Off
Preset
Preset
Voltage
Determined ON
Time Adjustable
Off
NUMBER OF
UVLO AND
PAIRS OF I/O
4 Monitors
with 1 I/O
4 Monitors
with 1 I/O
4 Monitors
with 1 I/O
4 Monitors
with 1 I/O
EN/EN
EN
FEATURES
Auto Restart,
Low Bias Current
Sleep
Auto Restart
Auto Restart, Open
Drain Sequenced
Outputs
Gates Independent
On as UVLO Valid
ISL6124
ISL6125
EN
EN
CMOS
CMO
Gate Drive
Open Drain
4 UVLO
4 UVLO
4 Gates
4 Open Drain
ISL6126
EN
CMOS
Gate Drive
4 UVLO
1 Gate
ISL6127
ISL6128
ISL6130
EN
EN
EN
CMOS
CMOS
TTL
Gate Drive
Gate Drive
Gate Drive
4 UVLO
1 EN
4 UVLO
2 EN
1 UVLO
1 EN
4 UVLO
2 UVLO
4 UVLO
4 Gates
2 Gates
1 Gate
4 Monitors
with 1 I/O
2 Monitors
with 2 I/O
4 Monitors
with 1 I/O
Auto Restart
Dual Redundant
Operation
Gates Independent
On as UVLO Valid
Low Bias Current
Sleep
FN9005 Rev 1.00
September 26, 2012
Page 5 of 23
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