USER’S MANUAL
HIP6501AEVAL1
Evaluation Board
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Connect the Input Power Supply
Ensuring that the supply is not plugged into the mains, or
that the AC switch is off (if provided), connect the main ATX
output connector to J1.
AN9846
Rev 2.00
Aug 1999
Introduction
The Advanced Configuration and Power Interface
specification (ACPI; [1]), written by a consortium
representing Intel, Microsoft and Toshiba, attempts to evolve
the current collection of power management methods and
configuration interfaces into a well-specified and unified
power management and configuration mechanism. The key
objective in the ACPI specification is to transfer all control of
power management and configuration functions to the
operating system, thus enabling Operating System Directed
Power Management (OSPM). ACPI-compliant systems will
benefit from a robust interface for configuring motherboard
devices, a versatile power management interface enabling a
wide variety of solutions with full operating-system support,
and not lastly, a realm of new, intelligent possibilities added
to the already broad span of PC uses.
The HIP6501A is the first Intersil IC to be used in conjunction
with a second chip to provide a complete ACPI-sanctioned
motherboard power regulation solution. The
HIP6501A/HIP6021 chip sets produce the processor core,
GTL bus, memory controller hub, and clock chip voltages, as
well as the SDRAM memory, 3.3V and 5V dual voltage
planes [2, 3] necessary for a complete PIII-Whitney system
implementation.
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Connect the Output Loads
Connect typical standby loads to all the evaluation board’s
outputs. Consult Table 1 for maximum loads supported by
the design of the HIP6501AEVAL1 in the configuration
received; consult the ‘HIP6501AEVAL1 Modifications’
chapter for information on modifying the evaluation board to
meet your special needs.
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Set Start-Up State (Active Is Recommended)
If start-up in active state is desired, ensure both ‘S3’ and ‘S5’
switches are in the off position (away from ‘S3’ or ‘S5’
marking). Ensure the ‘ATX ON’ switch is also in the off
position.
Set either the ‘S3’ or the ‘S5’ switch for start-up in either of
the standby states. IMPORTANT: only one switch needs to
be actuated, so select the standby state by turning on the
switch with that name - the signal conditioning circuitry
ensures correct S3 and S5 pin stimulation.
Operation
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Provide Bias Voltage to the Board
Plug the ATX supply into the mains. If the supply has an AC
switch, turn it on. The ‘5VSB’ (LP4) LED should light up,
indicating the presence of 5V standby voltage on board.
Quick Start Evaluation
IMPORTANT!
Given the specialized nature of the HIP6501A, the
HIP6501AEVAL1 board is meant to be evaluated only with
an ATX power supply. Furthermore, only an ACPI-ready ATX
supply can be used to power-up the evaluation board
(720mA capability on 5VSB output; ATX Specification v2.02,
[4]). Standard laboratory power supplies are not suitable for
powering up this evaluation board.
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Examine Start-Up Waveforms
Sleep state start-up is immediate following application of
bias voltage. Using an oscilloscope or other laboratory
equipment, you may study the ramp-up and/or regulation of
the controlled voltages, according to the specific JP1, 2
configuration previously set and the specific standby state
selected.
For start-up into an active state (standby switches set off
prior to application of bias voltage), flip on the ‘ATX ON’
switch. This will turn on the main ATX outputs and the
HIP6501A will start up into active state. Once turned on,
SW1 needs not be turned off until bias is removed from the
board.
Circuit Setup
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Set up JP1 and JP2
Before connecting the input ATX supply to the
HIP6501AEVAL1 board, consult the data sheet and set the
JP1 and JP2 configuration jumpers according to the
configuration you wish to emulate. This configuration is
latched in at power-up, but can be subsequently changed
during active state operation (S0, S1) or during a chip
shutdown (while PB1 is being pressed). See HIP6501A data
sheet for information on all the available configurations and
how to set them [5].
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Examine Output Quality Under Varying Loads
In either state (sleep or active) vary the output loads to
simulate computer loads typical of the specific operating
state the circuit is in.
AN9846 Rev 2.00
Aug 1999
Page 1 of 11
HIP6501AEVAL1
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Examine state transitions
For subsequent transitions into standby states, leave the main
ATX outputs enabled (SW1 on); the circuit will automatically
turn them off when entering a standby state. To enter a standby
state, turn on the respective switch. The ‘S3’ LED will light up
to indicate S3 standby state, while S5 state will illuminate both
‘S3’ and ‘S5’ LEDs. However, the HIP6501A will ignore any
illegal transition requests, such as from S3 state to S5 state or
vice versa, as shown in Figure 1.
Configuring Sleep State Support
Sleep state support on the 3.3V
DUAL
and 5V
DUAL
outputs is
user-configurable through jumpers JP1 and JP2 (consult data
sheet for sleep support details, [5]). The configuration can be
changed prior to 5VSB application, during active state
operation, as well as during chip shutdown (PB1 pressed).
During sleep states, the configuration is latched in and any
changes in the EN3VDL and EN5VDL pins’ logic status are
ignored.
HIP6501AEVAL1 Reference Design
FULL ACTIVE
S0
S1, S2
IDLE
General
The HIP6501AEVAL1 is built on 2-ounce, 4-layer, printed
circuit board (see last three pages of this application note for
layout plots). Most of the components specific to the evaluation
board alone, which are not needed in a real computer
application, are placed on the bottom side of the board.
Assuming the input supplies and the controlled output planes
have their own on-board filtering (capacitors), the only
components required to implement this ACPI 3-voltage
controller/regulator solution are contained within the white
rectangle surrounding the HIP6501A on the top side of the
board.
All the additional circuitry contained on board has the
role of duplicating the computer environment the chip would
operate in. Since this additional circuitry would clutter and
detract from the readability of the schematic, most of it was
grouped in two blocks, named “SIGNAL CONDITIONING” and
“FAULT LATCH”.
The board also contains a serpentine resistor which occupies
about 1/3 of both top and bottom sides of the board. The ATX
supply requires some minimum loading on the +5V output in
order to stay active; lack of this minimum loading causes the
ATX to shut down all its outputs, except +5VSB. This minimum
load is specified as 1A, but most supplies will stay active with
as little as 400-500mA. The embedded resistor should draw a
current of about 1A (typical). If the current draw is insufficient to
keep the power supply active, try reducing the value of the
embedded resistor. Shorting out the W1 footprint, on the back
side of the board, effectively shorts out 1/4 of the resistive
trace, increasing the current draw by 30%. Similarly, shorting
out W2 reduces the trace by 50%, thus doubling the current
draw from the +5V output. If either W1 or W2 are shorted, it is
advised that active state operation be reduced as to avoid
severe overheating of the board (in case the 5V current draw
exceeds 1A). For most, if not all cases, neither W1 nor W2
need be shorted.
ACTIVE
STATES
SLEEP
STATES
S3
STR
S4, S5
STD, SOFT-OFF
LEGEND:
STR - SUSPEND TO RAM
STD - SUSPEND TO DISK
- LEGAL TRANSITION
- ILLEGAL TRANSITION (REQUEST IGNORED BY THE HIP6501A)
FIGURE 1. HIP6501A LEGAL/ILLEGAL STATE TRANSITIONS
Fault Handling
In case of a FAULT condition (output under-voltage) occurring
while in active state (such as a suddenly shorted output), the
FAULT/SEL pin assesses a logic ‘high’, shutting down the ATX
supply’s main outputs. To recover from such a shutdown, press
the ‘SHUTDOWN/CLEAR FAULT’ button (PB1). Depressing
PB1 will initiate a soft-start sequence, thus clearing the FAULT,
and enabling the main ATX outputs.
If jumper JP3 (FAULT LATCH) is removed, the FAULT output
will not latch the circuit. The circuit appears to latch off because
the FAULT signal shuts down the ATX supply, cutting off the
input supply to the faulting output, and thus keeping it from
ever recovering from the fault condition.
However, it is not
recommended to test the circuit against output under-voltages
(output short-circuits) with JP3 removed.
Due to the very slow
response of the ATX supply in response to a shutdown
request, the external N/P-MOS switches (Q3A, Q3B, and Q4)
in use at the time of testing will usually fail as a result of
sustained over-current through the drain-source junction and
bond wires. The FAULT latch circuit acts on the SS pin directly,
shutting down the IC quickly. To protect the external switches it
is recommended that JP3 is shunted throughout the operation
of the board.
Design Envelope
Although different computer systems might have different
requirements, the HIP6501AEVAL1 was designed to meet the
maximum output loading described in Table 1. Note the fact
that the addition of all the sleep state output currents exceeds
the ATX 5VSB output capability (725mA). Real-life sleep state
current requirement on each of the outputs could be lower, and
their maximums should rarely all occur simultaneously. Output
AN9846 Rev 2.00
Aug 1999
Page 2 of 11
HIP6501AEVAL1
tolerances and current ratings (with the exception of the
2.5/3.3V
MEM
output current rating in sleep state) can be
adjusted by properly selecting the components external to the
HIP6501A.
TABLE 1. HIP6501AEVAL1 MAXIMUM OUTPUT LOADING
ACTIVE STATES
OUTPUT
VOLTAGE
2.5/3.3V
MEM
3.3V
DUAL
5V
DUAL
I
OUT
4A
3A
2.5A
dI
OUT
/dt
1A/s
0.2A/s
0.1A/s
SLEEP STATES
I
OUT
250mA
600mA
200mA
dI
OUT
/dt
1A/s
0.2A/s
0.1A/s
TOL.
(static/
dynamic)
5% / 9%
9% / 9%
9% / 9%
4>
3
2
1
5VSB
5V
DUAL
3.3V
DUAL
2.5V
MEM
The maximum current draw on the 2.5V
MEM
output systems
employing RDRAM memory) can be as high as 7-8A for short
periods of time during memory initialization. To avoid having to
design a high-current output which would be used at its fullest
potential only during a very short period of time, we
recommend reducing the memory clock speed during
initialization. This method should result in a significant
reduction in the current needed during initialization. This
current can then be delivered through a single external pass
transistor connected directly to the DRV2 pin.
Ch1 1.00V
BW
Ch3 1.00V
BW
T0
T1
Ch2 1.00V
BW
Ch4 1.00V
BW
T2
5.00ms
Ch4
2.98V
FIGURE 2. HIP6501AEVAL1 START-UP IN SLEEP STATE (S3)
WITH ALL OUTPUTS ENABLED
Active-State Start-Up
Figure 3 also shows a start-up sequence, but this time into
active state (S0,S1). As the enable pins only configure the
sleep state voltage support, this start-up sequence will be the
same, regardless of EN3VDL and EN5VDL status. In Figure 3,
SW1, SW2 and SW3 are all off and 5VSB is applied to the
board. Active state operation is enabled by switching on SW1,
just 3-4ms before T0. At time T0, the 12V input exceeds the
under-voltage threshold and the internal 50ms (typical) timer is
initiated. Between T0 and T1, the 3.3V
DUAL
and 5V
DUAL
outputs undergo a quasi soft-start, due to conduction through
the body diodes of the active
N-MOS switches (Q3A and Q3B). At time T1 the timer expires
and the two N-MOS transistors are turned on; simultaneously
the 2.5V
MEM
output begins a soft-start cycle, being charged up
through the external pass transistor, Q1.1B. The ramp-up of
the 2.5V
MEM
output ends at T2, when it reaches its regulation
limit.
12VIN
HIP6501AEVAL1 Performance
Figures 2-6 depict the evaluation board’s performance during a
few typical operational situations. To simulate minimum loading
conditions, unless otherwise specified, the outputs were
loaded with 65 resistive loads.
Sleep-State Start-Up
Figure 2 shows a typical start-up into S3 sleep state while all
outputs are enabled (EN3VDL = 0, EN5VDL = 1). As 5VSB is
applied to the board, SW1 and SW3 are off, while SW2 is on.
At time T0 the input supply exceeds the power-on-reset (POR)
threshold. Three milliseconds afterwards, at time T1, the soft-
start clamp is removed and the outputs start to ramp up toward
their target value, which they reach at time T2. The 5V
DUAL
output has a slightly different ramp-up due to the fact that it
undergoes a different soft-start than the remainder of the
output voltages. The 5V
DUAL
output is not actively regulated,
as is the case with the 2.5V
MEM
and 3.3V
DUAL
outputs in S3,
but rather switched on through a
P-MOS or PNP switch. An error amplifier is thus provided for
the 5V
DUAL
output just for the purpose of providing a smooth,
controlled output voltage rise. This error amplifier uses a
different, soft-start derived, control signal to achieve the
controlled ramp-up of the output.
5V
DUAL
3.3V
DUAL
4>
3
2
1
2.5V
MEM
T0
Ch1 1.00V
BW
Ch3 1.00V
BW
T1
Ch2 1.00V
BW
Ch4 2.00V
BW
T2
7.96V
10.00ms
Ch4
FIGURE 3. HIP6501AEVAL1 START-UP IN ACTIVE STATE
(S0,S1) WITH ALL OUTPUTS ENABLED
AN9846 Rev 2.00
Aug 1999
Page 3 of 11
HIP6501AEVAL1
State Transition
Figure 4 shows the transition from active state (S0,S1) to S3
sleep state. Prior to time T0, the evaluation board was
operating in active mode, with SW1 on and SW2 and SW3 off.
At time T0, SW2 is switched on, triggering the switch-over of
the output regulation from the active ATX output rails to the
5VSB supply, as well as the turn-off of the ATX. At time T1 the
ATX responds to the turn-off request, and the 5V output starts
to ramp down under the current draw caused by the embedded
5 serpentine resistor.
3.3VIN
4
1>
3.3V
DUAL
2>
2.5V
MEM
3>
5VIN
5V
DUAL
3.3V
DUAL
T0T1
T2
Ch1 200mV
BW
Ch3 200mV
BW
5V
DUAL
T3T4
T5
Ch2 200mV
BW
Ch4 200mV
BW
2.00ms
Ch4
3.19V
2.5V
MEM
FIGURE 5. HIP6501AEVAL1 ACTIVE STATE (S0,S1) OUTPUT
TRANSIENT RESPONSE (ALL OUTPUTS
ENABLED)
4>
3
2
1
T0
Ch1 1.00V
BW
Ch3 1.00V
BW
T1
Ch2 1.00V
BW
Ch4 1.00V
BW
2.00ms
Ch4
3.00V
Similar explanation accompanies the 5VDUAL output
waveform, except that the ATX 5V output could not be shown
due to measurement equipment limitations. However, the
voltage offset caused by the transient load application can be
identified as the product of 50m and 2.5A, resulting in 125mV
of voltage droop.
The situation is different with the 2.5VMEM output.
This output is actively regulated by the IC, and the resulting
output regulation is a combined effect of high dV/dt ripple
caused by the transient edges, decreased voltage overhead
for the pass NPN transistor due to ATX 3.3V ripple, as well as
DC accuracy of the internal circuitry. Under the combined
effects of all parameters listed above and with fairly scarce
amounts of capacitance present on board, the memory output
is still maintained within a 4% tolerance.
FIGURE 4. HIP6501AEVAL1 ACTIVE STATE (S0,S1) TO
STANDBY STATE (S3) TRANSITION WITH ALL
OUTPUTS ENABLED
The transition back from S3 sleep state to active state mirrors
the active-to-sleep state transition, above.
Transient Response
In Figure 5, all the outputs of the evaluation circuit are
subjected to simultaneous load transients while operating in
active state (S0, S1). Output loading of each output consists of
different frequency transients of amplitude equal to the
maximum active state current as defined in Table 1,
superimposed on a constant 50mA load. The output transients’
rate of change (dI/dt) also match the values described in Table
1. All outputs shown in the oscilloscope capture are DC offset
by their nominal value, and all are DC coupled. The rectangles
underneath each of the output waveforms indicate the duration
of each transient occurring on the respective output.
As it can be seen in Figure 5, the 3.3V
DUAL
output follows the
AC meandering of the ATX 3.3V output very accurately, being
separated only by the r
DS(ON)
of the N-MOS switch (Q3A).
During the transient loading, the 3.3VDUAL output develops a
DC offset, due to the voltage droop across Q3A. Specific to this
circuit and the particular circuit loading, the offset can easily be
identified as the product of 50m and 3A, resulting in 150mV
of voltage drop.
Output Short-Circuit Protection
Figure 6 depicts the circuit’s behavior in response to a sudden
output short-circuit (output under-voltage), applied in this
scope capture on the 2.5V
MEM
output, while operating in
active state. At time T0 a short-circuit is applied using an
electronic load - as a result, the 2.5V output starts to rapidly
discharge, crossing the falling under-voltage threshold (68% of
2.5 = 1.7V) at time T1. To avoid false triggers, the UV detector
is equipped with a 10s filter. As the UV event exceeds the
10s window, it triggers a fault response at time T2. The logic
high output on the FAULT/MSEL pin sets the external fault
latch circuitry which quickly discharges the SS capacitor just
below the chip shutdown level, reached at time T3. The chip
reset disables the fault reporting and the latch maintains the
circuit in a reset state. Depressing the CLEAR FAULT button
resets the latch and releases the circuit for operation.
AN9846 Rev 2.00
Aug 1999
Page 4 of 11
HIP6501AEVAL1
High dV/dt spikes present in the output voltage waveform
under highly dynamic load application (high dI/dt) are due to
the ESR and the ESL of the output capacitance. These spikes
coincide with the transient load’s rising and falling edges, and
decreasing their amplitude can be achieved by using lower
ESR/ESL output capacitors (such as surface-mount tantalum
capacitors), and/or the addition of more ceramic capacitors,
which have inherently low ESR/ESL.
The addition of more input-side capacitance and decreasing
the input-side capacitor banks’ ESR can also help in situations
where the input-side ripple is affecting the output regulation.
Such an example is the 3.3V ripple reducing the overhead
voltage available for Q1.1B, and thus inducing an output droop
component - in such instance, the addition of input-side
capacitance and reduction of the ESR component can reduce
the output excursion.
3.3VIN
SS
2.5V
MEM
FAULT
4>
3
2
1
T0
Ch1 500mV
BW
Ch3 500mV
BW
T1
T2
Ch2 500mV
BW
Ch4 1.00V
BW
T3
10.00s
Ch4
1.50V
FIGURE 6. HIP6501AEVAL1 2.5V
MEM
OUTPUT
UNDERVOLTAGE RESPONSE WHILE IN ACTIVE
STATE (S0, S1))
Conclusion
The HIP6501A is a sophisticated integrated circuit that
envelops all the required circuitry for ease of ACPI
implementation. The circuit employs intelligent switching
methods for smooth power plane transitions, noise immunity
circuitry for nuisance trip avoidance, and a direct interface to
the south bridge and logical circuitry for simplified control and
configuration.
HIP6501AEVAL1 Modifications
Setting the 2.5/3.3V
MEM
Output to 3.3V
The HIP6501AEVAL1 evaluation board ships populated for
RDRAM memory support, with the memory output set for 2.5V.
The HIP6501A, however, is designed for either 2.5V or 3.3V
memory output voltage. To change the memory output voltage
on the evaluation board perform the following steps:
• Remove Q1.1B, or lift both base and emitter pins off the
solder pads on the board
• Replace R3 with a 15k resistor
• Install an N-MOS, SO-8 transistor, HUF76113SK8 or
equivalent, in the provided Q1.2 footprint
With the above modifications, the memory output will be set to
3.3V. In this configuration, the output voltage obtainable in
active state is directly related to the ATX 3.3V output, the
memory output current, and the r
(DS)ON
of Q1.2, according to
the following equation:
V
MEM
=
V
IN
–
I
MEM
r
DS
ON
References
For Intersil documents available on the internet, see web site
http://www.intersil.com/
[1] Advanced Configuration and Power Interface
Specification, Revision 1.0, December 1996,
Intel/Microsoft/Toshiba. (http://www.teleport.com/~acpi/).
[2]
HIP6020 Data Sheet,
Intersil Corporation,
Document No. FN4683, 1999. (http://www.intersil.com/).
[3]
HIP6021 Data Sheet,
Intersil Corporation,
Document No., FN4684, 1999.
[4] ATX Specification, Version 2.02, October 1998, Intel
Corporation (http://www.teleport.com/~atx/).
[5]
HIP6501A Data Sheet,
1999, Intersil Corporation,
Document No. FN4749.
Improving Output Voltage Tolerance
The key to improving the output voltage tolerance is identifying
the parameters which affect it, and then taking steps toward
improving them.
As explained in the text accompanying Figure 5, the output DC
voltage droop on the 3.3V
DUAL
and 5V
DUAL
outputs under
applied load is due to the resistive losses across the N-MOS
switch’s own r
DS(ON)
- decreasing the r
DS(ON)
results in
reduced load-dependent voltage droop.
AN9846 Rev 2.00
Aug 1999
Page 5 of 11
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