Oscillator for Security and Surveillance Applications
The Smart Timing Choice
The Smart Timing Choice
Features
Applications
36 standard frequencies between 3.57 MHz and 80 MHz
100% pin-to-pin drop-in replacement to quartz-based XO
Excellent total frequency stability as low as ±20 PPM
Low power consumption of 3.6 mA typical
Standby mode for longer battery life
Fast startup time of 5 ms
LVCMOS/HCMOS compatible output
Industry-standard packages: 2.0 x 1.6, 2.5 x 2.0, 3.2 x 2.5, 5.0 x 3.2,
7.0 x 5.0 mm
Pb-free, RoHS and REACH compliant
Ideal for DVR, CCTV, IP CAM, security, cameras
Electrical Characteristics
[1, 2]
Parameter and Conditions
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
Typ.
Max.
Unit
MHz
PPM
PPM
Condition
36 standard frequencies between 3.57 MHz and 80 MHz
Inclusive of Initial tolerance at 25°C, 1st year aging at 25°C, and
variations over operating temperature, rated power supply
voltage and load.
Extended Commercial
Industrial
Contact
SiTime
for 1.5V support
Frequency Range
(Refer
to the frequency list page 6)
-20
-25
–
–
+20
+25
Frequency Stability and Aging
Operating Temperature Range
Operating Temperature Range
T_use
-20
-40
Supply Voltage
Vdd
1.62
2.25
2.52
2.7
2.97
2.25
Current Consumption
Idd
–
–
–
OE Disable Current
Standby Current
I_OD
I_std
–
–
–
–
–
Duty Cycle
Rise/Fall Time
DC
Tr, Tf
45
–
–
–
Output High Voltage
VOH
90%
–
–
1.8
2.5
2.8
3.0
3.3
–
3.8
3.6
3.4
–
–
2.6
1.4
0.6
–
1
1.3
–
–
+70
+85
1.98
2.75
3.08
3.3
3.63
3.63
4.5
4.2
3.9
4
3.8
4.3
2.5
1.3
55
2
2.5
2
–
°C
°C
V
V
V
V
V
V
mA
mA
mA
mA
mA
A
A
A
%
ns
ns
ns
Vdd
No load condition, f = 20 MHz, Vdd = 2.8V to 3.3V
No load condition, f = 20 MHz, Vdd = 2.5V
No load condition, f = 20 MHz, Vdd = 1.8V
Vdd = 2.5V to 3.3V, OE = GND, output is Weakly Pulled Down
Vdd = 1.8 V. OE = GND, output is Weakly Pulled Down
ST = GND, Vdd = 2.8V to 3.3V, Output is Weakly Pulled Down
ST = GND, Vdd = 2.5V, Output is Weakly Pulled Down
ST = GND, Vdd = 1.8V, Output is Weakly Pulled Down
All Vdds
Vdd = 2.5V, 2.8V, 3.0V or 3.3V, 20% - 80%
Vdd =1.8V, 20% - 80%
Vdd = 2.25V - 3.63V, 20% - 80%
IOH = -4 mA (Vdd = 3.0V or 3.3V)
IOH = -3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOH = -2 mA (Vdd = 1.8V)
IOL = 4 mA (Vdd = 3.0V or 3.3V)
IOL = 3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOL = 2 mA (Vdd = 1.8V)
Pin 1, OE or ST
Pin 1, OE or ST
Pin 1, OE logic high or logic low, or ST logic high
Pin 1, ST logic low
Supply Voltage and Current Consumption
LVCMOS Output Characteristics
Output Low Voltage
VOL
–
–
10%
Vdd
Input Characteristics
Input High Voltage
Input Low Voltage
Input Pull-up Impedence
VIH
VIL
Z_in
70%
–
–
2
–
–
87
–
–
30%
100
–
Vdd
Vdd
k
M
Notes:
1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.
2. Contact
SiTime
for custom drive strength to drive higher or multiple load, or SoftEdge™ option for EMI reduction.
SiTime Corporation
Rev. 1.02
990 Almanor Avenue
Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised March 20, 2013
SiT1604
Oscillator for Security and Surveillance Applications
The Smart Timing Choice
The Smart Timing Choice
Electrical Characteristics
[1, 2]
(continued)
Parameter and Conditions
Startup Time
Enable/Disable Time
Resume Time
Startup Time
RMS Period Jitter
RMS Phase Jitter (random)
Symbol
T_start
T_oe
T_resume
T_start
T_jitt
T_phj
Min.
–
–
–
–
–
–
–
–
Typ.
–
–
–
–
1.76
1.78
0.5
1.3
Max.
5
130
5
5
Jitter
3
3
0.9
2
ps
ps
ps
ps
f = 75 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V
f = 75 MHz, Vdd = 1.8V
f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz
f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz
Unit
ms
ns
ms
ms
Condition
Measured from the time Vdd reaches its rated minimum value
f = 110 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles
Measured from the time ST pin crosses 50% threshold
Measured from the time Vdd reaches its rated minimum value
Startup and Resume Timing
Notes:
1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.
2. Contact
SiTime
for custom drive strength to drive higher or multiple load, or SoftEdge™ option for EMI reduction.
Pin Description
Pin
Symbol
OE/ ST
1
22
Output
Enable
Standby
GND
OUT
VDD
Power
Output
Power
Open
[3]
:
Functionality
H or
specified frequency output
L: output is high impedance. Only output driver is disabled.
H or Open
[3]
: specified frequency output
L: output is low (weak pull down). Device goes to sleep mode. Supply
current reduces to I_std.
Electrical ground
[4]
Oscillator output
Power supply voltage
[4]
Top View
OE/ST
1
4
VDD
2
3
4
GND
2
3
OUT
Notes:
3. A pull-up resistor of <10 k between OE/ ST pin and Vdd is recommended in high noise environment.
4. A capacitor value of 0.1 µF between Vdd and GND is recommended.
Absolute Maximum
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual perfor-
mance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
VDD
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Junction Temperature
Min.
-65
-0.5
–
–
–
Max.
150
4
2000
260
150
Unit
°C
V
V
°C
°C
Thermal Consideration
Package
7050
5032
3225
2520
2016
JA, 4 Layer Board
(°C/W)
191
97
109
117
124
JA, 2 Layer Board
(°C/W)
263
199
212
222
227
JC, Bottom
(°C/W)
30
24
27
26
26
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.02
Page 2 of 7
www.sitime.com
SiT1604
Oscillator for Security and Surveillance Applications
The Smart Timing Choice
The Smart Timing Choice
Timing Diagram
90% Vdd, 2.5/2,8/3.3V devices
Vdd
95% Vdd, 1.8V devices
Vdd
Pin 4 Voltage
NO Glitch first cycle
ST Voltage
50% Vdd
T_resume
CLK Output
T_start
CLK Output
T_start: Time to start from power-off
T_resume: Time to resume from ST
Figure 1. Startup Timing (OE/ST Mode)
u
Vdd
50% Vdd
T_OE
CLK Output
Figure 2. Standby Resume Timing (ST Mode Only)
OE Voltage
Vdd
OE Voltage
50% Vdd
CLK Output
T_OE
HZ
T_OE: Time to re-enable the clock output
T_OE: Time to put the output drive in High Z mode
Figure 3. OE Enable Timing (OE Mode Only)
Figure 4. OE Disable Timing (OE Mode Only)
Notes:
5. SiT1604 supports no runt pulses and no glitches during startup or resume.
6. SiT1604 supports gated output which is accurate within rated frequency stability from the first cycle.
Rev. 1.02
Page 3 of 7
www.sitime.com
SiT1604
Oscillator for Security and Surveillance Applications
The Smart Timing Choice
The Smart Timing Choice
Dimensions and Patterns
Package Size – Dimensions (Unit: mm)
[7]
2.0 x 1.6 x 0.75 mm
2.0±0.05
#4
#3
#3
Recommended Land Pattern (Unit: mm)
[8]
0.65
#4
1.5
0.48
1.6±0.05
YXXXX
#1
#2
0.93
0.75±0.05
#2
#1
1.2
0.68
0.9
2.5 x 2.0 x 0.75 mm
1.9
2.5 ± 0.05
#4
#3
#3
1.00
#4
2.0 ± 0.05
1.1
0.5
YXXXX
#1
#2
1.5
#2
#1
0.75 ± 0.05
0.75
1.1
3.2 x 2.5 x 0.75 mm
3.2 ± 0.05
#4
#3
#3
2.1
#4
2.2
2.5 ± 0.05
0.9
0.75 ± 0.05
0.9
1.4
5.0 x 3.2 x 0.75 mm
2.54
5.0 ± 0.05
#4
#3
#3
2.39
#4
3.2 ± 0.05
0.8
0.75 ± 0.05
#2
#1
1.15
1.5
Notes:
7. Top marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the device.
8. A capacitor of value 0.1 µF between Vdd and GND is recommended.
Rev. 1.02
Page 4 of 7
1.6
#1
#2
1.1
YXXXX
2.2
1.2
#1
#2
#2
#1
0.7
YXXXX
1.9
1.0
0.8
www.sitime.com
SiT1604
Oscillator for Security and Surveillance Applications
The Smart Timing Choice
The Smart Timing Choice
Dimensions and Patterns
Package Size – Dimensions (Unit: mm)
[9]
7.0 x 5.0 x 0.90 mm
7.0 ± 0.05
5.08
Recommended Land Pattern (Unit: mm)
[10]
5.08
5.0 ± 0.05
2.6
YXXXX
1.1
3.81
0.90 ± 0.10
1.4
2.2
Notes:
9.Top marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the device.
10. A capacitor of value 0.1 µF between Vdd and GND is recommended.
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