HIGH SPEED
2K X 8 DUAL-PORT
STATIC RAM
WITH INTERRUPTS
Features
◆
◆
IDT71321SA/LA
IDT71421SA/LA
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
High-speed access
– Commercial: 20/25/35/55ns (max.)
– Industrial: 25/55ns (max.)
Low-power operation
– IDT71321/IDT71421SA
—
Active: 325mW (typ.)
—
Standby: 5mW (typ.)
– IDT71321/421LA
—
Active: 325mW (typ.)
—
Standby: 1mW (typ.)
Two
INT
flags for port-to-port communications
MASTER IDT71321 easily expands data bus width to 16-or-
more-bits using SLAVE IDT71421
On-chip port arbitration logic (IDT71321 only)
BUSY
output flag on IDT71321;
BUSY
input on IDT71421
Fully asynchronous operation from either port
Battery backup operation – 2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Available in 52-Pin PLCC, 52-Pin STQFP, 64-Pin TQFP, and
64-Pin STQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
A
10L
A
0L
(1,2)
I/O
Control
I/O
0R
-I/O
7R
BUSY
R
Address
Decoder
11
(1,2)
MEMORY
ARRAY
11
Address
Decoder
A
10R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
and
INTERRUPT
LOGIC
CE
R
OE
R
R/W
R
INT
L
(2)
INT
R
2691 drw 01
(2)
NOTES:
1. IDT71321 (MASTER):
BUSY
is open drain output and requires pullup resistor of 270Ω.
IDT71421 (SLAVE):
BUSY
is input.
2. Open drain output: requires pullup resistor of 270Ω.
FEBRUARY 2018
1
©2018 Integrated Device Technology, Inc.
DSC-2691/16
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Description
The IDT71321/IDT71421 are high-speed 2K x 8 Dual-Port Static
RAMs with internal interrupt logic for interprocessor communications.
The IDT71321 is designed to be used as a stand-alone 8-bit Dual-
Port Static RAM or as a "MASTER" Dual-Port Static RAM together
with the IDT71421 "SLAVE" Dual-Port in 16-bit-or-more word width
systems. Using the IDT MASTER/SLAVE Dual-Port Static RAM ap-
proach in 16-or-more-bit memory system applications results in full
speed, error-free operation without the need for additional discrete
logic.
Both devices provide two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by
CE,
permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 325mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each Dual-
Port typically consuming 200µW from a 2V battery.
The IDT71321/IDT71421 devices are packaged in 52-pin PLCC,
52-pin STQFP, 64-pin TQFP, and 64-pin STQFP.
Pin Configurations
(1,2,3)
I/O
3L
I/O
2L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
NC
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
20 19 18 17 16 15 14 13 12 11 10 9 8
21
7
6
22
5
23
4
24
3
25
2
26
1
27
71321/421
(4)
J52
52
28
51
29
50
30
49
31
48
32
47
33
34 35 36 37 38 39 40 41 42 43 44 45 46
I/O
1L
I/O
0L
A
9L
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
OE
L
A
10L
INT
L
BUSY
L
R/W
L
CE
L
V
CC
CE
R
R/W
R
BUSY
R
INT
R
A
10R
I/O
7R
NC
A
9R
A
8R
A
7R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
OE
R
2691 drw 02
INDEX
2
6.42
OE
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
N/C
A
7L
A
8L
A
9L
N/C
I/O
0L
I/O
1L
I/O
2L
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52 package body is approximately .75 in x .75 in x .17 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
PP64 package body is approximately 10mm x 10mm x 1.4mm.
4. This package code is used to reference the package diagram.
N/C
N/C
A
10R
INT
R
BUSY
R
R/W
R
CE
R
V
CC
V
CC
CE
L
R/W
L
BUSY
L
INT
L
A
10L
N/C
N/C
48 4746 45444342 41 40 39 38 3736 3534 33
32
49
50
31
51
30
52
29
53
28
54
27
55
26
56
25
71321/421
24
57
PN64 / PP64
(4)
58
23
59
22
60
21
61
20
62
19
63
18
64
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
N/C
A
7R
A
8R
A
9R
N/C
N/C
I/O
7R
I/O
6R
I/O
5R
I/O
4R
N/C
I/O
3R
I/O
2R
I/O
1R
I/O
0R
GND
GND
N/C
I/O
7L
I/O
6L
I/O
5L
I/O
4L
N/C
I/O
3L
2691 drw 03
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Pin Configurations (continued)
(1,2,3)
BUSY
R
42
A
0L
OE
L
A
10L
INT
L
BUSY
L
R/W
L
CE
L
V
CC
CE
R
R/W
R
44
43
INT
R
A
10R
41
40
INDEX
52
51
50
49
48
47
46
45
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
1
2
3
4
5
6
7
8
9
10
11
12
13
71321/421
PP52
(4)
39
38
37
36
35
34
33
32
31
30
29
28
27
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
N/C
I/O
7R
,
2691 drw 03a
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PP52 package body is approximately 10mm x 10mm x 1.4mm.
4. This package code is used to reference the package diagram.
22
23
I/O
2R
I/O
3R
I/O
5L
I/O
6L
I/O
7L
N/C
GND
I/O
0R
I/O
4L
14
15
16
17
18
19
20
21
I/O
4R
I/O
5R
I/O
6R
I/O
1R
25
26
24
Capacitance
(1)
Symbol
C
IN
C
OUT
(TA = +25°C, f = 1.0MHz) TQFP Only
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
2691 tbl 00
Recommended Operating
Temperature and Supply Voltage
(1,2)
Grade
Commercial
Industrial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
2691 tbl 02
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +7.0
Unit
V
Recommended DC Operating
Conditions
Symbol
V
CC
GND
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
2691 tbl 03
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
o
C
C
V
IH
V
IL
o
mA
2691 tbl 01
NOTES:
1. V
IL
(min.) = -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
CC
+ 10%.
3
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,4)
(V
CC
= 5.0V ± 10%)
71321X20
71421X20
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
CE
L
and
CE
R
= V
IL
,
Outputs Disabled
f = f
MAX
(2)
Test Condition
Version
COM'L
IND
COM'L
IND
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(2)
COM'L
IND
COM'L
IND
COM'L
IND
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
Typ.
110
110
____
____
71321X25
71421X25
Com'l
& Ind
Typ.
110
110
110
110
30
30
30
30
65
65
65
65
1.0
0.2
1.0
0.2
60
60
60
60
Max.
220
170
270
220
65
45
75
55
150
115
170
140
15
5
30
10
145
105
165
130
2691 tbl 04a
Max.
250
200
____
____
Unit
mA
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
and
CE
R
= V
IH
f = f
MAX
(2)
30
30
____
____
65
45
____
____
mA
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
65
65
____
____
165
125
____
____
mA
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(3)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(2)
1.0
0.2
____
____
15
5
____
____
mA
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
60
60
____
____
155
115
____
____
mA
71321X35
71421X35
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
CE
L
and
CE
R
= V
IL
,
Outputs Disabled
f = f
MAX
(2)
Test Condition
Version
COM'L
IND
COM'L
IND
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(2)
COM'L
IND
COM'L
IND
COM'L
IND
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
Typ.
80
80
____
____
71321X55
71421X55
Com'l
& Ind
Typ.
65
65
65
65
20
20
20
20
40
40
40
40
1.0
0.2
1.0
0.2
40
40
40
40
Max.
155
110
190
140
65
35
70
50
110
75
125
90
15
4
30
10
100
70
110
85
2691 tbl 04b
Max.
165
120
____
____
Unit
mA
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
and
CE
R
= V
IH
f = f
MAX
(2)
25
25
____
____
65
45
____
____
mA
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
50
50
____
____
125
90
____
____
mA
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(3)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(2)
1.0
0.2
____
____
15
4
____
____
mA
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
45
45
____
____
110
85
____
____
mA
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC
, and using “AC TEST CONDITIONS” of input
levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc = 5V, T
A
=+25°C for Typ and is not production tested. Vcc
DC
= 100mA (Typ)
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
4
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (V
CC
= 5.0V ± 10%)
71321SA
71421SA
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
(1)
Output Low Voltage (I/O
0
-I/O
7
)
Open Drain Output
Low Voltage (BUSY/INT)
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
CE
= V
IH
, V
OUT
= 0V to V
CC
,
V
CC
- 5.5V
I
OL
= 4mA
I
OL
= 16mA
I
OH
= -4mA
Min.
___
___
71321LA
71421LA
Min.
___
___
Max.
10
10
0.4
0.5
___
Max.
5
5
0.4
0.5
___
Unit
µA
µA
V
V
V
2691 tbl 05
___
___
___
___
2.4
2.4
NOTE:
1. At Vcc < 2.0V leakages are undefined.
Data Retention Characteristics
(LA Version Only)
Symbol
V
DR
I
CCDR
Parameter
V
CC
for Data Retention
Data Retention Current
V
CC
= 2.0V,
CE
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or VI
N
< 0.2V
t
CDR
(3)
t
R
(3)
Chip Deselect to Data Retention Time
Operation Recovery Time
COM'L
IND
Test Condition
Min.
2.0
____
____
Typ.
(1)
____
Max.
0
1500
4000
____
____
Unit
V
µA
µA
ns
ns
2691 tbl 06
100
100
____
____
0
t
RC
(2)
NOTES:
1. V
CC
= 2V, T
A
= +25°C, and is not production tested.
2. t
RC
= Read Cycle Time
3. This parameter is guaranteed but not production tested.
Data Retention Waveform
DATA RETENTION MODE
V
DR
≥
2.0V
V
CC
4.5V
t
CDR
4.5V
t
R
CE
V
IH
V
DR
V
IH
2691 drw 04
,
5
6.42
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
