ASAHI KASEI
[AK8815/16]
AK8815/16
NTSC/PAL Digital Video Encoder
GENERAL DESCRIPTION
The AK8815/16 is a digital video encoder which is developed for portable apparatus applications such as cellular
phone etc.. ITU-R BT.601 level compatible Y, Cb,and Cr signals which correspond to square pixel are encoded
into either NTSC or PAL compatible composite video signal. Interface is made in HSYNC-, VSYNC- synchronized
slave-mode operation. It is controlled via a 4-wire serial interface.
FEATURES
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NTSC-M, PAL-B, D, G, H, I encoding
Composite Video Output
Y:Cb:Cr 4:2:2 Square Pixel Data Input
H/V Slave Operation
Y filtering: 2 x over-sampling
C filtering: 4 x over-sampling
9-bit DAC
Macrovision Copy Protection Rev. 7.1 * (only AK8815 )
VBID ( CGMS-A ) Compatible
WSS Compatible
On-chip Quartz Crystal Oscillator circuit
Clock: Square Pixel data rate 24.5454 MHz ( NTSC ), 29.50 MHz ( PAL )
Device Control I / F : 4- wire Serial Bus Interface
On-chip Color Bar Output
Black Burst Output
Internal Operating Voltage: 2.7 V ~ 3.3 V
supplying Interface Power Supply ( 1.6 V ~ 2.0 V or 2.7 V ~ 3.3 V )
Power-down function
Monolithic CMOS
57 pin FBGA ( 5 mm sq ) ( lead-free package )
(*Note) This device is protected by U.S. patent numbers 4,631,603, 4,577,216, and 4,819,098, and other
intellectual rights. The use of Macrovision’s copy protection technology in the device must be authorized by
Macrovision and is intended for home and other limited pay-per -view use only, unless otherwise authorized in
written by Macrovision. Reverse engineering or disassembly is prohibited.
MS0331-E-00
1
2004 / 08
ASAHI KASEI
[AK8815/16]
BLOCK DIAGRAM
XTI/CLKIN
XTO
CLKINV
RSTN PDN
CS
SCLK
SDI
SDO
VREF
CLKMD
CLK
Generator
u-p I/F
Register
Timing Controller
VREF
Generator
IREF
VSYNC
HSYNC
D[7:0
]
Synchronization Control
SYNC
Generator
Y
Cb
Cr
U
Cos
SubCarrier
Generator
Sin
V
C
Chroma
LPF Filter
(x 2 Interpolator)
TEST
Logic
TEST ATPG
UD[4:0]
VBID & WSS
Macrovision
Input Data Control
Y
LPF Filter
(x 2 Interpolator)
9-bit
DAC
VIDEOOUT
CLKOUT
Cb/Cr
LPF Filter
(x 2 Interpolator)
Color Bar &
Background
Color Control
PVDD2 PVSS2 PVDD1 PVSS1
DVDD DVSS XVDD
AVDD AVSS
MS0331-E-00
2
2004 / 08
ASAHI KASEI
[AK8815/16]
ORDERING GUIDE
AK8815/16VG 57 pin FBGA
PIN LAYOUT
57pin FBGA
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
Bottom View
MS0331-E-00
3
2004 / 08
ASAHI KASEI
[AK8815/16]
PIN FUNCTIONAL DESCRIPTION (preliminary)
No.
Pin Name
I/O
Function
Quartz crystal resonator connection pin ( to be grounded via a 18 pF capacitor as shown
in the recommended circuit ).
NTSC: 24.5454 MHz / PAL: 29.50 MHz
Hi-Z input is acceptable to this pin at PDN = L.
Input from an external crystal oscillator should be connected to this pin.
Quartz crystal resonator connection pin ( to be grounded via a 22 pF capacitor as shown
in the recommended circuit ).
NTSC: 25.5454 MHz / PAL: 29.50 MHz
DVSS level is output on this pin at PDN = L.
Clock Mode setting pin. Should be connected to either DVDD or DGND.
GND connection: when a crystal resonator is used
XVDD connection: when an external crystal oscillator is used
Clock output pin. NTSC: 24.5454 MHz / PAL: 29.50 MHz
This becomes Hi-Z output at PDN =L.
“L “ : data is latched with rising edge.
“H” : data is latched with falling edge.
Internal clock is inverted (internal operation timing edge is inverted. CLKOUT is not
affected). Connect to either DVDD or DGND.
Power Down Pin. After returning from PD mode to normal operation, RESET Sequence
should be done to AK8815/16.
“L “(GND level): Power-down
“H “: normal operation
Reset input pin. In order to initialize the device , an initialization must be made in
accordance with the reset sequence.
“L “ : reset
“H “ : reset
Hi-Z input is acceptable to this pin at PDN = L.
Serial Data clock input pin. 15 MHz ( max )
Hi-Z input is acceptable to this pin at PDN = L.
Serial Data input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Serial Data output pin.
This becomes high output at PDN = L.
This pin interfaces one-to-one with a controller through a dedicated pin.
Serial Data Chip Enable signal input pin.
This pin interfaces one-to-one with a controller through a dedicated pin.
L : disabled condition ( un-selected )
H : enabled condition ( selected )
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin (MSB).
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin (LSB).
Hi-Z input is acceptable to this pin at PDN = L.
Horizontal SYNC signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Vertical SYNC signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
On-chip VREF output pin. AVSS level is output on this pin at PDN = L.
Connect this pin to Analog Ground via a 0.1 uF or larger capacitor.
A7
XTI/CLKIN
I
B6
XTO
O
B5
B9
B7
CLKMD
CLKOUT
CLKINV
I
O
I
J6
PDN
I
J5
RSTN
I
J4
H4
H3
SCLK
SDI
SDO
I
I
O
H5
CS
I
H8
G8
H9
G9
F8
E8
D8
D9
J7
H7
B3
D7
D6
D5
D4
D3
D2
D1
D0
HSYNC
VSYNC
VREF
I
I
I
I
I
I
I
I
I
I
O
MS0331-E-00
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2004 / 08
ASAHI KASEI
[AK8815/16]
A2
C1
C2
A5
B2
B1
D1
A6
A3
F1
F9
E2
E9
C8
C9
J3
H2
A4
B8
A8
H1
J2
G1
G2
E1
D2
A1
A9
J1
J9
B4
H6
J8
F2
C3
IREF
VIDEOOUT
AVDD
XVDD
AVDD
AVSS
DVSS
DVSS
AVSS
DVDD
DVDD
DVSS
DVSS
PVDD1
PVSS1
PVDD2
PVSS2
AVSS
TEST
ATPG
DVDD
UD4
UD3
UD2
UD1
UD0
NC
NC
NC
NC
NC
NC
NC
NC
N.C.
O
O
P
P
P
G
G
G
G
P
P
G
G
P
G
P
G
G
I
I
P
O
O
O
I/O
I/O
-
-
-
-
-
-
-
-
-
IREF output pin. Connect this pin to Analog ground via a 12 Kohm resistor
( better than +/_ 1% accuracy ).
Video output pin. Connect this pin to Analog ground via a 390 ohm resistor
resistor ( better than +/_ 1% accuracy ).
Analog power supply pin.
Power supply pin for crystal ( for XTAL ).
Analog power supply pin.
Analog ground pin.
Digital ground pin.
Crystal ground connection pin ( set DVSS [0 V] ).
Analog ground pin.
Digital power supply ( digital core power supply )
Digital power supply ( digital core power supply )
Digital ground pin ( digital core ground )
Digital ground pin ( digital core ground )
Power supply pin for chip pad.
I / F power supply for CLKOUT, D[7:0], HSYNC, VSYNC
Ground pin for PVDD1
Power supply pin for chip pad.
I / F power supply for PDN, RSTN, SDO, SDI, CS, SCLK.
Ground pin for PVDD2
Ground pin for the substrate biasing
Connect to Analog Ground.
For normal operation, connect to ground.
For normal operation, connect to ground.
Digital power supply
Test output pin. For normal operation, left un-connected ( NC ).
Test output pin. For normal operation, left un-connected ( NC ).
Test output pin. For normal operation, left un-connected ( NC ).
Test I/O pin. For normal operation, left un-connected ( NC ).
Test I/O pin. For normal operation, left un-connected ( NC ).
NC pin.
NC pin.
NC pin.
NC pin.
NC pin
NC pin.
NC pin.
NC pin.
Index pin
MS0331-E-00
5
2004 / 08
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