If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Tolerance (Note 2)
Machine Model
Human Body Model
Supply Voltage (V –V )
Output Short Circuit to V
Output Short Circuit to V
Storage Temp. Range
+
−
+
−
Junction Temp. (T
J
max) (Note 5)
Mounting Temperature
Infrared or Convection (20 sec)
150˚C
235˚C
Operating Ratings
(Note 1)
200V
1500V
5.5V
(Note 3)
(Note 4)
−65˚C to 150˚C
Supply Voltage
Temperature Range
Thermal Resistance (θ
JA
)
5-pin SC70-5
5-pin SOT23-5
478˚C/W
265˚C/W
2.7V to 5.0V
−40˚C
≤
T
J
≤
85˚C
2.7V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for T
its apply at the temperature extremes.
Symbol
V
O
Output Swing
Parameter
J
= 25˚C, V
+
= 2.7V, V
−
= 0V, V
O
= V
+
/2 and R
L
>
1 MΩ.
Boldface
lim-
Conditions
R
L
= 10kΩ to 1.35V
Typ
(Note 6)
V
+
−0.01
0.06
Limit
(Note 7)
V
+
−0.1
0.18
170
Units
V
min
V
max
µA
max
%
MHz
Deg
dB
I
S
Supply Current
Resistor Ratio Matching
80
1
C
L
= 200pF
1
60
10
GBWP
Φ
m
G
m
Gain-Bandwidth Product
Phase Margin
Gain Margin
5V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for T
apply at the temperature extremes.
Symbol
V
O
Output Swing
Parameter
J
= 25˚C, V
+
= 5V, V
−
= 0V, V
O
= V
+
/2 and R
L
>
1 MΩ.
Boldface
limits
Conditions
R
L
= 2kΩ to 2.5V
Typ
(Note 6)
V
+
−0.04
0.12
R
L
= 10kΩ to 2.5V
V
+
−0.01
0.065
Limit
(Note 7)
V
+
−0.3
V
+
−0.4
0.3
0.4
V
+
−0.1
V
+
−0.2
0.18
0.28
5
10
250
350
Units
V
min
V
max
V
min
V
max
mA
min
mA
min
µA
max
%
MHz
Deg
dB
V/µs
I
O
Output Current
Sourcing, V
O
= OV
Sinking, V
O
= 5V
60
160
130
1
I
S
Supply Current
Resistor Ratio Matching
GBWP
φm
G
m
SR
Gain-Bandwidth Product
Phase Margin
Gain Margin
Slew Rate
C
L
= 200pF
1
60
10
(Note 8)
1
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is in-
tended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2:
Human body model, 1.5kΩ in series with 100pF. Machine model, 0Ω in series with 100pF.
www.national.com
2
LMV111
5V Electrical Characteristics
(Continued)
Note 3:
Shorting circuit output to V
+
will adversely affect reliability.
Note 4:
Shorting circuit output to V
-
will adversely affect reliability.
Note 5:
The maximum power dissipation is a function of T
J(max)
,
θ
JA
, and T
A
. The maximum allowable power dissipation at any ambient temperature is
P
D
= (T
J(max)
–T
A
)/θ
JA
. All numbers apply for packages soldered directly into a PC board.
Note 6:
Typical values represent the most likely parametric norm.
Note 7:
All limits are guaranteed by testing or statistical analysis.
Note 8:
Connected as voltage follower with 3V step input. Number specified is the slower of the positive and negative slew rates.
Typical Performance Characteristics
25˚C.)
Supply Current vs.
Supply Voltage
(Unless otherwise specified, V
S
= +5V, single supply, T
A
=
Sourcing Current vs.
Output Voltage
Sourcing Current vs.
Output Voltage
DS101262-1
DS101262-2
DS101262-3
Sinking Current vs.
Output Voltage
Sinking Current vs.
Output Voltage
Open Loop Frequency vs.
Response
DS101262-4
DS101262-5
DS101262-6
Open Loop Frequency vs.
Response
Open Loop Frequency
Response vs. Temperature
Gain and Phase vs.
Capacitive Load
DS101262-7
DS101262-8
DS101262-9
3
www.national.com
LMV111
Typical Performance Characteristics
25˚C.) (Continued)
Gain and Phase vs.
Capacitive Load
Slew Rate vs.
Supply Voltage
(Unless otherwise specified, V
S
= +5V, single supply, T
A
=
Non-Inverting Large Signal Pulse
Response
DS101262-10
DS101262-11
DS101262-12
Non-Inverting Small Signal Pulse
Response
Inverting Large Signal Pulse
Response
Inverting Small Signal Pulse
Response
DS101262-13
DS101262-14
DS101262-15
Open Loop Output
Impedance vs. Frequency
Short Circuit Current vs.
Temperature (Sinking)
Short Circuit Current vs.
Temperature (Sourcing)
DS101262-16
DS101262-17
DS101262-18
www.national.com
4
LMV111
Typical Performance Characteristics
25˚C.) (Continued)
Output Voltage Swing vs.
Supply Voltage
(Unless otherwise specified, V
S
= +5V, single supply, T
A
=
DS101262-22
Application Section
The LMV111 integrates a rail-to-rail op amp and a V
+
/2 bias
circuit into one ultra tiny package. With its small footprint and
reduced component count for bias network, it enables the
design of smaller portable electronic products, such as cellu-
lar phones, pagers, PDAs, PCMCIA cards, etc. In addition,
the integration solution minimizes printed circuit board stray
capacitance, and reduces the complexity of circuit design.
The core op amp of this family is National’s LMV321.
1.0 Supply Bypassing
The application circuits in this datasheet do not show the
power supply connections and the associated bypass ca-
pacitors for simplification. When the circuits are built, it is al-
ways required to have bypass capacitors. Ceramic disc ca-
pacitors (0.1µF) or solid tantalum (1µF) with short leads, and
located close to the IC are usually necessary to prevent in-
terstage coupling through the power supply internal imped-
ance. Inadequate bypassing will manifest itself by a low fre-
quency oscillation or by high frequency instabilities.
Sometimes, a 10µF (or larger) capacitor is used to absorb
low frequency variations and a smaller 0.1µF disc is paral-
leled across it to prevent any high frequency feedback
through the power supply lines.
2.0 Input Voltage Range
The input voltage should be within the supply rails. The ESD
protection circuitry at the input of the device includes a diode
between the input pin and the negative supply pin. Driving
the input more than 0.6V (at 25˚C) beyond the negative sup-
ply will turn on the diode and cause signal distortions.
3.0 Capacitive Load Tolerance
The LMV111 can directly drive 200pF capacitive load with
unity gain without oscillation. The unity-gain follower is the
most sensitive configuration to capacitive loading. Direct ca-
pacitive loading reduces the phase margin of amplifiers. The
combination of the amplifier’s output impedance and the ca-
pacitive load induces phase lag. This results in either an un-
derdamped pulse or oscillation. To drive a heavier capacitive
load, a resistive isolation can be used as shown in
Figure 1.
DS101262-23
FIGURE 1. Resistive Isolation of a Heavy Capacitive
Load
The isolation resistor R
iso
and the C
L
form a pole to increase
stability by adding more phase margin to the overall system.
The desired performance depends on the value of R
iso
. A
50Ω to 100Ω isolation resistor is recommended for initial
嵌入式系统
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