Data Sheet
January 2005
™
FW802C Low-Power PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Distinguishing Features
Compliant with
IEEE
Standard 1394a-2000,
IEEE Standard for a High Performance Serial
Bus
Amendment 1.
Low-power consumption during powerdown or
microlow-power sleep mode.
Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders.
While unpowered and connected to the bus, the
device will not drive TPBIAS on a connected port
even if receiving incoming bias voltage on that port.
Does not require external filter capacitors for PLL.
Does not require a separate 5 V supply for 5 V link
controller interoperability.
Interoperable across 1394 cable with 1394 physical
layers (PHY) using 5 V supplies.
Interoperable with 1394 link-layer controllers using
5 V supplies.
1394a-2000 compliant common-mode noise filter
on incoming TPBIAS.
Powerdown features to conserve energy in battery-
powered applications include the following:
— Device powerdown pin.
— Link interface disable using LPS.
— Inactive ports power down.
— Automatic microlow-power sleep mode during
suspend.
Interface to link-layer controller supports Annex J
electrical isolation as well as bus-keeper isolation.
®
™
Supports connection debounce.
Supports multispeed packet concatenation.
Supports PHY pinging and remote PHY access
packets.
Fully supports suspend/resume.
Supports PHY-link interface initialization and reset.
Supports 1394a-2000 register set.
Supports LPS/link-on as a part of PHY-link inter-
face.
Supports provisions of
IEEE
1394-1995
Standard
for a High Performance Serial Bus.
Fully interoperable with
FireWire
®
and
i.LINK
®
implementations of
IEEE
1394-1995.
Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V.
Provides separate cable bias and driver termination
voltage supply for each port.
Other Features
48-pin TQFP package. (Lead-free package also
available. See ordering information on page 25.)
Single 3.3 V supply operation.
Data interface to link-layer controller provided
through 2/4/8 parallel lines at 50 Mbits/s.
25 MHz crystal oscillator and PLL provide a 50 MHz
link-layer controller clock as well as transmit/receive
data at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
Multiple separate package signals provided for ana-
log and digital supplies and grounds.
Features
Provides two fully compliant cable ports at
100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
Fully supports 1394 Open HCI requirements.
Supports arbitrated short bus reset to improve
utilization of the bus.
Supports ack-accelerated arbitration and fly-by con-
catenation.
FW802C Low-Power PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
Table of Contents
Contents
Page
Distinguishing Features ............................................................................................................................................ 1
Features ................................................................................................................................................................... 1
Other Features ......................................................................................................................................................... 1
Description................................................................................................................................................................ 3
Signal Information..................................................................................................................................................... 6
Application Information ........................................................................................................................................... 11
Crystal Selection Considerations............................................................................................................................ 12
Load Capacitance ............................................................................................................................................ 13
Adjustment to Crystal Loading ......................................................................................................................... 13
Crystal/Board Layout ........................................................................................................................................ 13
1394
Application Support Contact Information ....................................................................................................... 13
Absolute Maximum Ratings.................................................................................................................................... 14
Electrical Characteristics ........................................................................................................................................ 15
Timing Characteristics ............................................................................................................................................ 18
Timing Waveforms.................................................................................................................................................. 19
Internal Register Configuration............................................................................................................................... 20
Outline Diagrams.................................................................................................................................................... 25
48-Pin TQFP .................................................................................................................................................... 25
Ordering Information............................................................................................................................................... 25
List of Figures
Figures
Page
Figure 1. Block Diagram ........................................................................................................................................... 5
Figure 2. Pin Assignments........................................................................................................................................ 6
Figure 3. Typical External Component Connections .............................................................................................. 11
Figure 4. . Typical Port Termination Network ......................................................................................................... 12
Figure 5. . Crystal Circuitry ..................................................................................................................................... 13
Figure 6. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms ............................................................. 19
Figure 7. Dn, CTLn Output Delay Relative to SYSCLK Waveforms....................................................................... 19
List of Tables
Tables
Page
Table 1. . Signal Descriptions................................................................................................................................... 7
Table 2. . Absolute Maximum Ratings.................................................................................................................... 14
Table 3. . Analog Characteristics............................................................................................................................ 15
Table 4. . Driver Characteristics ............................................................................................................................. 16
Table 5. . Device Characteristics............................................................................................................................ 17
Table 6. . Switching Characteristics ....................................................................................................................... 18
Table 7. . Clock Characteristics............................................................................................................................. 18
Table 8. . PHY Register Map for the Cable Environment ...................................................................................... 20
Table 9. . PHY Register Fields for the Cable Environment .................................................................................... 20
Table 10. . PHY Register Page 0: Port Status Page ............................................................................................. 22
Table 11. . PHY Register Port Status Page Fields ................................................................................................ 23
Table 12. . PHY Register Page 1: Vendor Identification Page .............................................................................. 24
Table 13. . PHY Register Vendor Identification Page Fields ................................................................................. 24
2
Agere Systems Inc.
Data Sheet
January 2005
FW802C Low-Power PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
four (for S200), or eight (for S400) parallel streams,
resynchronized to the local system clock, and sent to
the associated LLC. The received data is also trans-
mitted (repeated) out of the other active (connected)
cable ports.
Both the TPA and TPB cable interfaces incorporate
differential comparators to monitor the line states dur-
ing initialization and arbitration. The outputs of these
comparators are used by the internal logic to deter-
mine the arbitration status. The TPA channel monitors
the incoming cable common-mode voltage. The value
of this common-mode voltage is used during arbitra-
tion to set the speed of the next packet transmission.
In addition, the TPB channel monitors the incoming
cable common-mode voltage for the presence of the
remotely supplied twisted-pair bias voltage. This moni-
tor is called bias-detect.
The TPBIAS circuit monitors the value of incoming
TPA pair common-mode voltage when local TPBIAS is
inactive. Because this circuit has an internal current
source and the connected node has a current sink, the
monitored value indicates the cable connection status.
This monitor is called connect-detect.
Both the TPB bias-detect monitor and TPBIAS con-
nect-detect monitor are used in suspend/resume
signaling and cable connection detection.
The PHY provides a 1.86 V nominal bias voltage for
driver load termination. When seen through a cable by
a remote receiver, this bias voltage indicates the pres-
ence of an active connection. The value of this bias
voltage has been chosen to allow interoperability
between transceiver chips operating from 5 V or 3 V
nominal supplies. This bias voltage source should be
stabilized by using an external filter capacitor of
approximately 0.33
µF.
The transmitter circuitry, the receiver circuitry, and the
twisted-pair bias voltage circuity are all disabled with a
powerdown condition. The powerdown condition
occurs when the PD input is high. The port transmitter
circuitry, the receiver circuitry, and the TPBIAS output
are also disabled when the port is disabled, sus-
pended, or disconnected.
The line drivers in the PHY operate in a high-imped-
ance current mode and are designed to work with
external 112
Ω
line-termination resistor networks. One
network is provided at each end of each twisted-pair
cable. Each network is composed of a pair of series-
connected 56
Ω
resistors. The midpoint of the pair of
resistors that is directly connected to the twisted-pair A
(TPA) signals is connected to the TPBIAS voltage sig-
nal. The midpoint of the pair of resistors that is
Description
The Agere Systems FW802C device provides the ana-
log physical layer functions needed to implement a
two-port node in a cable-based
IEEE
1394-1995 and
IEEE
1394a-2000 network.
Each cable port incorporates two differential line trans-
ceivers. The transceivers include circuitry to monitor
the line conditions as needed for determining connec-
tion status, for initialization and arbitration, and for
packet reception and transmission. The PHY is
designed to interface with a link-layer controller (LLC).
The PHY requires either an external 24.576 MHz crys-
tal or crystal oscillator. The internal oscillator drives an
internal phase-locked loop (PLL) that generates the
required 393.216 MHz reference signal. The
393.216 MHz reference signal is internally divided to
provide the 49.152 MHz, 98.304 MHz, and
196.608 MHz clock signals that control transmission of
the outbound encoded strobe and data information.
The 49.152 MHz clock signal is also supplied to the
associated LLC for synchronization of the two chips
and is used for resynchronization of the received data.
The powerdown function, when enabled by the PD sig-
nal high, stops operation of the PLL and disables all
circuitry except the cable-not-active (CNA) signal
circuitry.
The PHY supports an isolation barrier between itself
and its LLC. When /ISO is tied high, the link interface
outputs behave normally. When /ISO is tied low, inter-
nal differentiating logic is enabled, and the outputs
become short pulses that can be coupled through a
capacitor or transformer as described in the
IEEE
1394-1995 Annex J. To operate with bus-keeper
isolation, the /ISO pin of the FW802C must be tied
high.
Data bits to be transmitted through the cable ports are
received from the LLC on two, four, or eight data lines
(D[0:7]), and are latched internally in the PHY in syn-
chronization with the 49.152 MHz system clock. These
bits are combined serially, encoded, and transmitted at
98.304 Mbits/s, 196.608 Mbits/s, or 393.216 Mbits/s as
the outbound data-strobe information stream. During
transmission, the encoded data information is transmit-
ted differentially on the TPA and TPB cable pair(s).
During packet reception, the TPA and TPB transmit-
ters of the receiving cable port are disabled and the
receivers for that port are enabled. The encoded data
information is received on the TPA and TPB cable
pair. The received data-strobe information is decoded
to recover the receive clock signal and the serial data
bits. The serial data bits are split into two (for S100),
Agere Systems Inc.
3
FW802C Low-Power PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet
January 2005
When the power supply of the PHY is removed while
the twisted-pair cables are connected, the PHY trans-
mitter and receiver circuitry is designed to present a
high impedance to the cable in order to not load the
TPBIAS signal voltage on the other end of the cable.
Whenever the TBA±/TPB± signals are wired to a con-
nector, they must be terminated using the normal
termination network (See Figure 4). This is required for
reliable operation. For those applications, when one of
the FW802C’s ports is not wired to a connector, those
unused ports may be left unconnected without normal
termination. When a port does not have a cable con-
nected, internal connect-detect circuitry will keep the
port in a disconnected state.
Note:
All gap counts on all nodes of a 1394 bus must
be identical. The software accomplishes this by
issuing PHY configuration packets (see Section
4.3.4.3 of the
IEEE
1394a-2000 standard) or by
issuing two bus resets, which resets the gap
counts to the maximum level (3Fh).
The link power status (LPS) signal works with the
C/LKON signal to manage the LLC power usage of the
node. The LPS signal indicates that the LLC of the
node is powered up or powered down. If LPS is inac-
tive for more than 1.2
µs
and less than 25
µs,
the
PHY/link interface is reset. If LPS is inactive for greater
than 25
µs,
the PHY will disable the PHY/link interface
to save power. FW802C continues its repeater func-
tion even when the PHY/link interface is disabled. If
the PHY then receives a link-on packet, the C/LKON
signal is activated to output a 6.114 MHz signal that
can be used by the LLC to power itself up. Once the
LLC is powered up, the LPS signal communicates this
to the PHY and the PHY/link interface is enabled. The
C/LKON signal is turned off when LPS is active or
when a bus reset occurs, provided the interrupt that
caused C/LKON is not present.
When the PHY/link interface is in the disabled state,
the FW802C will automatically enter a low-power
mode if all ports are inactive (disconnected, disabled,
or suspended). In this low-power mode, the FW802C
disables its PLL and also disables parts of its refer-
ence circuitry depending on the state of the ports
(some reference circuitry must remain active in order
to detect incoming TP bias). The lowest power con-
sumption (the microlow-power sleep mode) is attained
when all ports are either disconnected or disabled with
the ports interrupt enable bit (see Table 11) cleared.
The FW802C will exit the low-power mode when the
LPS input is asserted high or when a port event occurs
that requires the FW802C to become active in order to
respond to the event or to notify the LLC of the event
Description
(continued)
directly connected to the twisted-pair B (TPB) signals
is coupled to ground through a parallel RC network
with recommended resistor and capacitor values of 5
kΩ and 220 pF, respectively.
The value of the external resistors are specified to
meet the
IEEE
1394 standard specifications when con-
nected in parallel with the internal receiver circuits.
The driver output current, along with other internal
operating currents, is set by an external resistor. This
resistor is connected between the R0 and R1 signals
and has a value of 2.49 kΩ
±
1%.
The FW802C supports suspend/resume as defined in
the
IEEE
1394a-2000 specification. The suspend
mechanism allows an FW802C port to be put into a
suspended state. In this state, a port is unable to
transmit or receive data packets; however, it remains
capable of detecting connection status changes and
detecting incoming TPBias. When all ports of the
FW802C are suspended, all circuits except the bias
voltage reference generator and the bias detection cir-
cuits are powered down, resulting in significant power
savings. The use of suspend/resume is recommended.
As an input, the C/LKON signal indicates whether a
node is a contender for bus manager. When the
C/LKON signal is asserted, it means the node is a con-
tender for bus manager. When the signal is not
asserted, it means that the node is not a contender.
The C bit corresponds to bit 20 in the self-ID packet
(see Section 4.3.4.1 of the
IEEE
1394a-2000 standard
for additional details).
The power class (Pwr_class) bits of the self-ID packet
have a default value of 000, i.e., power class 0. These
bits can be read and modified through the LLC using
Figure 5B-1 (PHY Register Map) and Section 4.3.4.1
of the
IEEE
1394a-2000 standard. See Table 8 of this
document for the address space of the Pwr_class
register.
A powerdown signal (PD) is provided to allow a power-
down mode where most of the PHY circuits are
powered down to conserve energy in battery-powered
applications. The internal logic in FW802C is reset as
long as the powerdown signal is asserted. A cable sta-
tus signal (CNA) provides a high output when none of
the twisted-pair cable ports are receiving incoming
bias voltage. This output is not debounced. The CNA
output can be used to determine when to power the
PHY down or up. In the powerdown mode, all circuitry
is disabled except the CNA circuitry. It should be noted
that when the device is powered down, it does not act
in a repeater mode.
4
Agere Systems Inc.
Data Sheet
January 2005
FW802C Low-Power PHY 1394a-2000
Two-Cable Transceiver/Arbiter Device
Two of the FW802C’s signals are used to set up vari-
ous test conditions used only during the device
manufacturing process. These signals (SE and SM)
should be connected to V
SS
for normal operation.
Description
(continued)
(e.g., incoming bias or disconnection is detected on a
suspended port, a new connection is detected on a
nondisabled port, etc.). When the FW802C is in the
low-power mode, the SYSCLK output will become
active (and the PHY/link interface will be initialized and
become operative) within 3 ms after LPS is asserted
high.
CPS
LPS
/ISO
CNA
SYSCLK
LREQ
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
LINK
INTERFACE
I/O
TPA0+
TPA0–
ARBITRATION
AND
CONTROL
STATE
MACHINE
LOGIC
RECEIVED
DATA
DECODER/
RETIMER
BIAS
VOLTAGE
AND
CURRENT
GENERATOR
R0
R1
TPBIAS0
CABLE PORT 0
TPB0+
TPB0–
C/LKON
SE
SM
PD
TPA1+
TPA1–
TPBIAS1
TPB1+
TPB1–
/RESET
TRANSMIT
DATA
ENCODER
CABLE PORT 1
CRYSTAL
OSCILLATOR,
PLL SYSTEM,
AND
CLOCK
GENERATOR
XI
XO
5-5459.f (F)
Figure 1. Block Diagram
Agere Systems Inc.
5
NXP MCU
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