HSP45256
TM
Data Sheet
May 1999
FN2814.4
Binary Correlator
The Intersil HSP45256 is a high-speed, 256 tap binary
correlator. It can be configured to perform one-dimensional
or two-dimensional correlations of selectable data precision
and length. Multiple HSP45256’s can be cascaded for
increased correlation length. Unused taps can be masked
out for reduced correlation length.
The correlation array consists of eight 32-tap stages. These
may be cascaded internally to compare 1, 2, 4 or 8-bit input
data with a 1-bit reference. Depending on the number of bits
in the input data, the length of the correlation can be up to
256, 128, 64, or 32 taps. The HSP45256 can also be
configured as two separate correlators with window sizes
from 4 by 32 to 1 by 128 each. The mask register can be
used to prevent any subset of the 256 bits from contributing
to the correlation score.
The output of the correlation array (correlation score) feeds
the weight and sum logic, which gives added flexibility to the
data format. In addition, an offset register is provided so that
a preprogrammed value can be added to the correlation
score. This result is then passed through a user
programmable delay stage to the cascade summer. The
delay stage simplifies the cascading of multiple correlators
by compensating for the latency of previous correlators.
The Binary Correlator is configured by writing a set of control
registers via a standard microprocessor interface. To simplify
operation, both the control and reference registers are
double buffered. This allows the user to load new mask and
reference data while the current correlation is in progress.
Features
• Reconfigurable 256 Stage Binary Correlator
• 1-Bit Reference x 1, 2, 4, or 8-Bit Data
• Separate Control and Reference Interfaces
• 25.6, 33MHz Versions
• Configurable for 1-D and 2-D Operation
• Double Buffered Mask and Reference
• Programmable Output Delay
• Cascadable
• Standard Microprocessor Interface
Applications
• Radar/Sonar
• Spread Spectrum Communications
• Pattern/Character Recognition
- Error Correction Coding
Ordering Information
PART NUMBER
HSP45256JC-25
HSP45256JC-33
HSP45256GC-25
HSP45256GC-33
HSP45256JI-25
HSP45256JI-33
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
-40 to 85
-40 to 85
PACKAGE
84 Ld PLCC
84 Ld PLCC
85 Ld PGA
85 Ld PGA
84 Ld PLCC
84 Ld PLCC
PKG.
NO.
N84.1.15
N84.1.15
G85.A
G85.A
N84.1.15
N84.1.15
Block Diagram
DOUT
DOUT0-7
DIN0-7
DREF0-7
256 TAP
CORRELATION
ARRAY
DREFOUT
CSCORE
WEIGHT
AND SUM
MUX
AUXOUT0-8
DCONT0-7
CONTROL
A0-2
DELAY
CASCADE
SUMMER
CASOUT0-12
CASIN0-12
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
HSP45256
Pin Descriptions
SYMBOL
V
CC
GND
DIN0-7
PLCC PIN NUMBER
16, 33, 63
14, 35, 55, 70, 77
17-24
I
TYPE
The +5V power supply pin.
Ground.
The DIN0-7 bus consists of eight single data input pins. The assignment of the active pins is
determined by the configuration. Data is loaded synchronous to the rising edge of CLK. DIN0
is the LSB.
The DOUT0-7 bus is the data output of the correlation array. The format of the output is de-
pendent on the window configuration and bit weighting. DOUT0 is the LSB.
System Clock. Positive edge triggered.
CASIN0-12 allows multiple correlators to be cascaded by connecting CASOUT0-12 of one
correlator to CASIN0-12 of another. The CASIN bus is added internally to the correlation
score to form CASOUT. CASIN0 is the LSB.
CASOUT0-12 is the output correlation score. This value is the delayed sum of all the 256
taps of one chip and CASIN0-12. When the part is configured to act as two independent cor-
relators, CASOUT0-8 represents the correlation score for the first correlator while the sec-
ond correlation score is available on the AUXOUT0-8 bus. In this configuration, the
cascading feature is no longer an option. CASOUT0 is the LSB.
OEC is the output enable for CASOUT0-12. When OEC is high, the output is three-stated.
Processing is not interrupted by this pin (active low).
TXFR is a synchronous clock enable signal that allows the loading of the reference and mask
inputs from the preload register to the correlation array. Data is transferred on the rising edge
of CLK while TXFR is low (active low).
DREF0-7 is an 8-bit wide data reference input. This is the input data bus used to load the
reference data. RLOAD going active initiates the loading of the reference registers. This in-
put bus is used to load the reference registers of the correlation array. The manner in which
the reference data is loaded is determined by the window configuration. If the window con-
figuration is 1 x 256, the reference bits are loaded one at a time over DREF7. When the
HSP45256 is configured as an 8 x 32 array, the data is loaded into all stages in parallel. In
this case, DREF7 is the reference data for the first stage and DREF0 is the reference data
for the eighth stage. The contents of the reference data registers are not affected by chang-
ing the window configuration. DREF0 is the LSB.
RLOAD enables loading of the reference registers. Data on DREF0-7 is loaded into the pre-
load registers on the rising edge of RLOAD. This data is transferred into the correlation array
by TXFR (active low).
DCONT0-7 is the control data input which is used to load the mask bit for each tap, as well
as the configuration registers. The mask data is sequentially loaded into the eight stages in
the same manner as the reference data. DCONT0 is the LSB.
CLOAD enables the loading of the data on DCONT0-7. The destination of this data is con-
trolled by A0-2 (active low).
A0-2 is a 3-bit address that determines what function will be performed when CLOAD is ac-
tive. This address bus is set up with respect to the rising edge of the load signal, CLOAD. A0
is the LSB.
AUXOUT0-8 is a 9-bit bus that provides either the data reference output in the single corre-
lation configuration or the 9-bit correlation score of the second correlator, in the dual corre-
lator configuration. When the user programs the chip to be two separate correlators, the
score of the second correlator is output on this bus. When the user has programmed the chip
to be one correlator, AUXOUT0-7 represents the reference data out, with the state of
AUXOUT8 undefined. AUXOUT0 is the LSB.
The OEA signal is the output enable for the AUXOUT0-8 output. When OEA is high, the out-
put is disabled. Processing is not interrupted by this pin (active low).
DESCRIPTION
DOUT0-7
CLK
CASIN0-12
60-62, 64-68
15
1-13
O
I
I
CASOUT0-12
69, 71-76, 78-83
O
OEC
TXFR
84
36
I
I
DREF0-7
25-32
I
RLOAD
34
I
DCONT0-7
41-48
I
CLOAD
A0-2
37
38-40
I
I
AUXOUT0-8
50-54, 56-59
O
OEA
49
I
4
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