INTEGRATED CIRCUITS
74LVT374
3.3V Octal D-type flip-flop; positive-edge
trigger (3-State)
Product specification
Supersedes data of 1996 Feb 08
IC23 Data Handbook
1998 Feb 19
Philips
Semiconductors
Philips Semiconductors
Product specification
3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)
74LVT374
FEATURES
•
Inputs and outputs on opposite side of package allow easy
•
3-State outputs for bus interfacing
•
Common output enable
•
TTL input and output switching levels
•
Input and output interface capability to systems at 5V supply
•
Bus-hold data inputs eliminate the need for external pull-up
•
Live insertion/extraction permitted
•
No bus current loading when output is tied to 5V bus
•
Power-up 3-State
•
Power-up reset
•
Latch-up protection exceeds 500mA per JEDEC Std 17
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
resistors to hold unused inputs
interface to microprocessors
DESCRIPTION
The 74LVT374 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74LVT374 is an 8-bit, edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE) control
gates.
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the clock operation.
When OE is Low, the stored data appears at the outputs. When OE
is High, the outputs are in the High-impedance “OFF” state, which
means they will neither drive nor load the bus.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
CP to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF;
V
CC
= 3.3V
V
I
= 0V or 3.0V
Outputs disabled;
V
I/O
= 0V or 3.0V
Outputs disabled;
V
CC
= 3.6V
TYPICAL
3.2
3.5
4
7
0.13
UNIT
ns
pF
pF
mA
ORDERING INFORMATION
PACKAGES
20-Pin Plastic SOL
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVT374 D
74LVT374 DB
74LVT374 PW
NORTH AMERICA
74LVT374 D
74LVT374 DB
74LVT374PW DH
DWG NUMBER
SOT163-1
SOT339-1
SOT360-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
OE
D0-D7
FUNCTION
Output enable input (active-Low)
Data inputs
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
1
3, 4, 7, 8,
13, 14, 17,
18
2, 5, 6, 9,
12, 15, 16,
19
11
10
20
Q0-Q7
CP
GND
V
CC
Data outputs
Clock pulse input (active rising edge)
Ground (0V)
Positive supply voltage
GND 10
SA00110
1998 Feb 19
2
853-1826 18985
Philips Semiconductors
Product specification
3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)
74LVT374
LOGIC SYMBOL
3
4
7
8
13 14 17
18
LOGIC SYMBOL (IEEE/IEC)
1
11
EN
C1
D0 D1 D2 D3 D4 D5 D6 D7
11
1
CP
OE
3
4
7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8
13
2
5
6
9
12 15 16
19
14
17
1D
2
5
6
9
12
15
16
19
SA00111
18
SA00112
FUNCTION TABLE
INPUTS
OE
L
L
L
H =
h =
L =
l =
NC=
X =
Z =
↑
=
↑
=
CP
↑
↑
↑
Dn
l
h
X
INTERNAL
REGISTER
L
H
NC
OUTPUTS
Q0 – Q7
L
H
NC
Hold
Disable outputs
OPERATING MODE
Load and read register
H
X
X
NC
Z
High voltage level
High voltage level one set-up time prior to the Low-to-High clock transition
Low voltage level
Low voltage level one set-up time prior to the Low-to-High clock transition
No change
Don’t care
High impedance “off” state
Low-to-High clock transition
not a Low-to-High clock transition
LOGIC DIAGRAM
D0
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
D
D
D
D
D
D
D
D
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
11
CP
1
OE
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
SA00113
1998 Feb 19
3
Philips Semiconductors
Product specification
3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)
74LVT374
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Output in High state
Storage temperature range
–64
–65 to 150
°C
V
O
< 0
Output in Off or High state
Output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +7.0
–50
–0.5 to +7.0
128
mA
UNIT
V
mA
V
mA
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
O
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Input voltage
High-level output current
Low-level output current
Low-level output current; current duty cycle
≤
50%, f
≥
1kHz
Input transition rise or fall rate; outputs enabled
Operating free-air temperature range
–40
PARAMETER
MIN
2.7
0
2.0
0.8
–32
32
mA
64
10
+85
ns/V
°C
MAX
3.6
5.5
V
V
V
V
mA
UNIT
1998 Feb 19
4
Philips Semiconductors
Product specification
3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)
74LVT374
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
V
IK
Input clamp voltage
V
CC
= 2.7V; I
IK
= –18mA
V
CC
= 2.7 to 3.6V; I
OH
= –100µA
V
OH
High-level output voltage
V
CC
= 2.7V; I
OH
= –8mA
V
CC
= 3.0V; I
OH
= –32mA
V
CC
= 2.7V; I
OL
= 100µA
V
CC
= 2.7V; I
OL
= 24mA
V
OL
Low-level output voltage
V
CC
= 3.0V; I
OL
= 16mA
V
CC
= 3.0V; I
OL
= 32mA
V
CC
= 3.0V; I
OL
= 64mA
V
RST
Power-up output low voltage
5
V
CC
= 3.6V; I
O
= 1mA; V
I
= GND or V
CC
V
CC
= 0 or 3.6V; V
I
= 5.5V
I
I
Input l k
I
t leakage current
t
V
CC
= 3.6V; V
I
= V
CC
or GND
V
CC
= 3.6V; V
I
= V
CC
V
CC
= 3.6V; V
I
= 0
I
OFF
I
HOLD
Output off current
Bus Hold current A inputs
7
Current into an output in the
High state when V
O
> V
CC
Power up/down 3-State output
current
3
3-State output High current
3-State output Low current
V
CC
= 0V; V
I
or V
O
= 0 to 4.5V
V
CC
= 3V; V
I
= 0.8V
V
CC
= 3V; V
I
= 2.0V
V
CC
= 0V to 3.6V; V
CC
= 3.6V
I
EX
I
PU/PD
I
OZH
I
OZL
I
CCH
I
CCL
I
CCZ
∆I
CC
Additional supply current per
input pin
2
Quiescent supply current
3
V
O
= 5.5V; V
CC
= 3.0V
V
CC
≤
1.2V; V
O
= 0.5V to V
CC
; V
I
= GND or V
CC
;
OE/OE = Don’t care
V
CC
= 3.6V; V
O
= 3V; V
I
= V
IL
or V
IH
V
CC
= 3.6V; V
O
= 0.5V; V
I
= V
IL
or V
IH
V
CC
= 3.6V; Outputs High, V
I
= GND or V
CC,
I
O =
0
V
CC
= 3.6V; Outputs Low, V
I
= GND or V
CC,
I
O =
0
V
CC
= 3.6V; Outputs Disabled; V
I
= GND or V
CC,
I
O =
0
6
V
CC
= 3V to 3.6V; One input at V
CC
-0.6V,
Other inputs at V
CC
or GND
75
–75
±500
60
1
1
1
0.13
3
0.13
0.1
125
±100
5
–5
0.19
12
0.19
0.2
mA
mA
µA
µA
µA
µA
Control pins
Data pins
4
V
CC
-0.2
2.4
2.0
TYP
1
–0.9
V
CC
-0.1
2.5
2.2
0.1
0.3
0.25
0.3
0.4
0.13
1
±0.1
0.1
–1
1
150
–150
µA
0.2
0.5
0.4
0.5
0.55
0.55
10
±1
1
-5
±100
µA
µA
A
V
V
V
MAX
–1.2
V
UNIT
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25°C.
2. This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND
3. This parameter is valid for any V
CC
between 0V and 1.2V with a transition time of up to 10msec. From V
CC
= 1.2V to V
CC
= 3.3V
±
0.3V a
transition time of 100µsec is permitted. This parameter is valid for T
amb
= 25°C only.
4. Unused pins at V
CC
or GND.
5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
6. I
CCZ
is measured with outputs pulled to V
CC
or down to GND.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 19
5
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