TM
HM-6504
4096 x 1 CMOS RAM
Description
The HM-6504 is a 4096 x 1 static CMOS RAM fabricated
using self-aligned silicon gate technology. The device uti-
lizes synchronous circuitry to achieve high performance and
low power operation.
On-chip latches are provided for addresses, data input and
data output allowing efficient interfacing with microprocessor
systems. The data output can be forced to a high impedance
state for use in expanded memory arrays.
Gated inputs allow lower operating current and also elimi-
nate the need for pull up or pull down resistors. The
HM-6504 is a fully static RAM and may be maintained in any
state for an indefinite period of time.
Data retention supply voltage and supply current are guaran-
teed over temperature.
March 1997
Features
• Low Power Standby. . . . . . . . . . . . . . . . . . . 125µW Max
• Low Power Operation . . . . . . . . . . . . . .35mW/MHz Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
• TTL Compatible Input/Output
• Three-State Output
• Standard JEDEC Pinout
• Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max
• 18 Lead Package for High Density
• On-Chip Address Register
• Gated Inputs - No Pull Up or Pull Down Resistors
Required
Ordering Information
120ns
-
HM1-6504S-9
24501BVA
810240IVA
-
200ns
HM3-6504B-9
HM1-6504B-9
-
8102403VA
-
300ns
HM3-6504-9
HM1-6504-9
-
8102405VA
HM4-6504-9
TEMP. RANGE
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-
-
-40
o
C to+85
o
C
PDIP
CERDIP
JAN #
SMD #
CLCC
PACKAGE
PKG. NO.
E18.3
F18.3
F18.3
F18.3
J18.B
Pinouts
HM-6504 (PDIP, CERDIP)
TOP VIEW
A0
A1
A2
A3
A4
A5
Q
W
GND
1
2
3
4
5
6
7
8
9
18 V
CC
17 A6
16 A7
15 A8
14 A9
13 A10
12 A11
11 D
10 E
V
CC
18
PIN
A
E
W
D
Q
DESCRIPTION
Address Input
Chip Enable
Write Enable
Data Input
Data Output
A2
A3
A4
A5
Q
3
4
5
6
7
HM-6504 (CLCC)
TOP VIEW
A1
A0
A6
17
16
15
14
13
12
8
W
9
GND
10
E
11
D
A7
A8
A9
A10
A11
2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN2994.1
126
HM-6504
Functional Diagram
LSB
A8
A7
A6
A0
A1
A2
A
LATCHED
ADDRESS
REGISTER
L
6
GATED
ROW
DECODER
G
64
G
D
Q
A
GATED COLUMN
DECODER AND
DATA I/O
D
Q
Q
A
64 x 64
MATRIX
64
A
6
D
D
Q
LATCH
L
LATCH
L
W
LATCH
L
6
A
L
LATCHED
ADDRESS
REGISTER
6
A
E
L
D
Q
LATCH
LSB A11 A5 A4 A3 A9 A10
NOTES:
13. All lines active high-positive logic.
14. Three-state Buffers: A high
→
output active.
15. Control and Data Latches: L low
→
Q = D and Q latches on rising edge of L.
16. Address Latches: Latch on falling edge of E.
17. Gated Decoders: Gate on rising edge of G.
127
HM-6504
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to V
CC
+0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
θ
JC
Thermal Resistance (Typical)
θ
JA
o
C/W
CERDIP Package . . . . . . . . . . . . . . . . 75
15
o
C/W
o
C/W
PDIP Package . . . . . . . . . . . . . . . . . . . 75
N/A
o
C/W
CLCC Package . . . . . . . . . . . . . . . . . . 90
33
o
C/W
Maximum Storage Temperature Range . . . . . . . . .-65
o
C to +150
o
C
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300
o
C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
HM-6504S-9, HM-6504B-9, HM-6504-9 . . . . . . . .-40
o
C to +85
o
C
HM-6504B-8, HM-6504-8 . . . . . . . . . . . . . . . . . .-55
o
C to +125
o
C
DC Electrical Specifications
V
CC
= 5V
±10%;
T
A
= -40
o
C to +85
o
C (HM-6504B-9, HM-6504-9)
T
A
= -55
o
C to +125
o
C (HM-6504B-8, HM-6504-8)
SYMBOL
ICCSB
PARAMETER
Standby Supply Current
HM-6504-9
HM-6504-8
ICCOP
Operating Supply
Current (Note 1)
Data Retention Supply
Current
HM-6504-9
HM-6504-8
VCCDR
II
IOZ
VIL
VIH
VOL
VOH1
VOH2
Data Retention Supply Voltage
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage (Note 2)
MIN
-
-
-
MAX
25
50
7
UNITS
µA
µA
mA
µA
µA
V
µA
µA
V
V
V
V
V
VI = V
CC
or GND, V
CC
= 5.5V
VO = V
CC
or GND, V
CC
= 5.5V
V
CC
= 4.5V
V
CC
= 5.5V
IO = 2.0mA, V
CC
= 4.5V
IO = -1.0mA, V
CC
= 4.5V
IO = -100µA, V
CC
= 4.5V
TEST CONDITIONS
IO = 0mA, E = V
CC
-0.3V,
V
CC
= 5.5V
E = 1MHz, IO = 0mA, VI = GND,
V
CC
= 5.5V
IO = 0mA, V
CC
= 2.0V, E = V
CC
ICCDR
-
-
2.0
-1.0
-1.0
-0.3
V
CC
-2.0
-
2.4
V
CC
-0.4
15
25
-
+1.0
+1.0
0.8
V
CC
+0.3
0.4
-
-
Capacitance
T
A
= +25
o
C
SYMBOL
CI
CO
NOTES:
1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
PARAMETER
Input Capacitance (Note 2)
Output Capacitance (Note 2)
MAX
8
10
UNITS
pF
pF
TEST CONDITIONS
f = 1MHz, All measurements are
referenced to device GND
128
HM-6504
AC Electrical Specifications
V
CC
= 5V
±10%;
T
A
= -40
o
C to +85
o
C (HM-6504S-9, HM-6504B-9, HM-6504-9)
T
A
= -55
o
C to +125
o
C (HM-6504B-8, HM-6504-8)
HM-6504S
SYMBOL
(1)
(2)
(3)
HM-6504B
MIN
-
-
5
MAX
200
220
-
HM-6504
MIN
-
-
5
MAX
300
320
-
UNITS
ns
ns
ns
TEST
CONDITIONS
(Notes 1, 3)
(Notes 1, 3, 4)
(Notes 2, 3)
PARAMETER
Chip Enable Access Time
Address Access Time
Chip Enable Output Enable
Time
Chip Enable Output Disable
Time
Chip Enable Pulse Negative
Width
Chip Enable Pulse Positive
Width
Address Setup Time
Address Hold Time
Write Enable Pulse Width
Write Enable Pulse Setup
Time
Early Write Pulse Setup
Time
Write Enable Read Mode
Setup Time
Early Write Pulse Hold Time
Data Setup Time
Early Write Data Setup Time
Data Hold Time
Early Write Data Hold Time
Read or Write Cycle Time
MIN
-
-
5
MAX
120
120
-
TELQV
TAVQV
TELQX
(4)
TEHQZ
-
50
-
80
-
100
ns
(Notes 2, 3)
(5)
TELEH
120
-
200
-
300
-
ns
(Notes 1, 3)
(6)
TEHEL
50
-
90
-
120
-
ns
(Notes 1, 3)
(7)
(8)
(9)
(10)
TAVEL
TELAX
TWLWH
TWLEH
0
40
20
70
-
-
-
-
20
50
60
150
-
-
-
-
20
50
80
200
-
-
-
-
ns
ns
ns
ns
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(11)
TWLEL
0
-
0
-
0
-
ns
(Notes 1, 3)
(12)
TWHEL
0
-
0
-
0
-
ns
(Notes 1, 3)
(13)
(14)
(15)
(16)
(17)
(18)
TELWH
TDVWL
TDVEL
TWLDX
TELDX
TELEL
40
0
0
25
25
170
-
-
-
-
-
-
60
0
0
60
60
290
-
-
-
-
-
-
80
0
0
80
80
420
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
NOTES:
1. Input pulse levels: 0.8V to V
CC
- 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
1 TTL gate equivalent, C
L
= 50pF (min) - for C
L
greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. V
CC
= 4.5V and 5.5V.
4. TAVQV = TELQV + TAVEL.
129
HM-6504
Timing Waveforms
(7)
TAVEL
A
(6)
TEHEL
E
(1) TELQV
(3)
TELQX
(8)
TELAX
(7)
TAVEL
NEXT ADD
TELEH
(5)
TELEL (18)
TEHEL
(6)
ADD VALID
(4) TEHQZ
VALID DATA OUTPUT
HIGH Z
Q
HIGH Z
HIGH
W
TIME
REFERENCE
-1
0
1
2
3
4
5
FIGURE 11. READ CYCLE
TRUTH TABLE
INPUTS
TIME REFERENCE
-1
0
1
2
3
4
5
H
L
L
E
H
W
X
H
H
H
H
X
H
A
X
V
X
X
X
X
V
OUTPUT
Q
Z
Z
X
V
V
Z
Z
Memory Disabled
Cycle Begins, Addresses are Latched
Output Enabled
Output Valid
Read Accomplished
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)
FUNCTION
The address information is latched in the on-chip registers
on the falling edge of E (T = 0). Minimum address set-up and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1) the output becomes
enabled but the data is not valid until during time (T = 2). W
must remain high for the read cycle. After the output data
has been read, E may return high (T = 3). This will disable
the output buffer and all input and ready the RAM for the
next memory cycle (T = 4).
130
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