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74ABT16821A
20-bit bus-interface D-type flip-flop; positive-edge trigger;
3-state
Rev. 03 — 16 March 2010
Product data sheet
1. General description
The 74ABT16821A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT16821A has two 10-bit, edge-triggered registers, with each register coupled to
a 3-state output buffer. The two sections of each register are controlled independently by
the clock (nCP) and output enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding flip-flops Q output.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors.
The active-LOW output enable (nOE) controls all ten 3-state buffers independent of the
register operation. When nOE is LOW, the data in the register appears at the outputs.
When nOE is HIGH, the outputs are in high-impedance OFF-state, which means they will
neither drive nor load the bus.
2. Features and benefits
20-bit positive-edge triggered register
Multiple V
CC
and GND pins minimize switching noise
Live insertion and extraction permitted
Output capability: +64 mA and
−32
mA
Power-up 3-state
Power-up reset
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
NXP Semiconductors
74ABT16821A
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74ABT16821ADL
74ABT16821ADGG
−40 °C
to +85
°C
−40 °C
to +85
°C
Name
SSOP56
TSSOP56
Description
plastic shrink small outline package; 56 leads;
body width 7.5 mm
plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
Version
SOT371-1
SOT364-1
Type number
4. Functional diagram
1
56
1OE
1CP
EN2
C1
EN4
C3
1D
2
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
1Q9
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
28
2OE
29
2CP
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
3D
4
001aae855
Fig 1.
IEC logic symbol
74ABT16821A_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 16 March 2010
2 of 16
NXP Semiconductors
74ABT16821A
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state
55
54
52
51
49
48
47
45
44
43
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9
56
1
1CP
1OE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
2
3
5
6
8
9
10
12
13
14
42
41
40
38
37
36
34
33
31
30
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9
29
28
2CP
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
15
16
17
19
20
21
23
24
26
27
001aae856
Fig 2.
Logic symbol
nD0
D
nD1
D
nD2
D
nD3
D
nD4
D
nD5
D
nD6
D
nD7
D
nD8
D
nD9
D
CP Q
nCP
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
nQ9
001aae857
Fig 3.
Logic diagram
74ABT16821A_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 16 March 2010
3 of 16
NXP Semiconductors
74ABT16821A
20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state
5. Pinning information
5.1 Pinning
74ABT16821A
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1
2
3
4
5
6
7
8
9
56 1CP
55 1D0
54 1D1
53 GND
52 1D2
51 1D3
50 V
CC
49 1D4
48 1D5
47 1D6
46 GND
45 1D7
44 1D8
43 1D9
42 2D0
41 2D1
40 2D2
39 GND
38 2D3
37 2D4
36 2D5
35 V
CC
34 2D6
33 2D7
32 GND
31 2D8
30 2D9
29 2CP
001aae854
1Q6 10
GND 11
1Q7 12
1Q8 13
1Q9 14
2Q0 15
2Q1 16
2Q2 17
GND 18
2Q3 19
2Q4 20
2Q5 21
V
CC
22
2Q6 23
2Q7 24
GND 25
2Q8 26
2Q9 27
2OE 28
Fig 4.
Pin configuration
74ABT16821A_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 16 March 2010
4 of 16
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