Features

◆

HIGH-SPEED 2.5V

512/256K x 18

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

◆

IDT70T633/1S

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial: 8/10/12/15ns (max.)

– Industrial: 10/12ns (max.)

RapidWrite Mode simplifies high-speed consecutive write

cycles

Dual chip enables allow for depth expansion without

external logic

IDT70T633/1 easily expands data bus width to 36 bits or

more using the Master/Slave select when cascading more

than one device

M/S = V

IH

for

BUSY

output flag on Master,

M/S = V

IL

for

BUSY

input on Slave

Busy and Interrupt Flags

◆

Functional Block Diagram

UB

L

LB

L

Full hardware support of semaphore signaling between

ports on-chip

On-chip port arbitration logic

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Sleep Mode Inputs on both ports

Supports JTAG features compliant to IEEE 1149.1 in

BGA-208 and BGA-256 packages

Single 2.5V (±100mV) power supply for core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 256-ball Ball Grid Array, 144-pin Thin Quad

Flatpack and 208-ball fine pitch Ball Grid Array

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

UB

R

LB

R

R/

W

L

B

E

0

L

B

E

1

L

B

E

1

R

B

E

0

R

R/

W

R

CE

0L

CE

1L

CE

0R

CE

1R

OE

L

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

OE

R

512/256K x 18

MEMORY

ARRAY

I/O

0L

- I/O

17L

Din_L

Din_R

I/O

0R

- I/O

17R

A

18L

(1)

A

0L

Address

Decoder

ADDR_L

ADDR_R

Address

Decoder

A

18R

(1)

A

0R

TDI

OE

L

CE

0L

CE

1L

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

OE

R

CE

0R

CE

1R

TDO

JTAG

TCK

TMS

TRST

R/W

L

R/W

R

BUSY

L(2,3)

SEM

L

INT

L(3)

ZZ

(4)

ZZ

L

ZZ

R

NOTES:

CONTROL

LOGIC

1. Address A

18

x is a NC for IDT70T631.

2.

BUSY

is an input as a Slave (M/S=V

IL

) and an output when it is a Master (M/S=V

IH

).

3

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx,

INTx,

M/S and the

sleep mode pins themselves (ZZx) are not affected during sleep mode.

BUSY

R(2,3)

M/S

SEM

R

INT

R(3)

5670 drw 01

JANUARY 2009

DSC-5670/6

1

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Description

The IDT70T633/1 is a high-speed 512/256K x 18 Asynchronous

Dual-Port Static RAM. The IDT70T633/1 is designed to be used as a

stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MAS-

TER/SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the

IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider

memory system applications results in full-speed, error-free operation

without the need for additional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access for

reads or writes to any location in memory. An automatic power down

feature controlled by the chip enables (either

CE

0

or CE

1

) permit the

on-chip circuitry of each port to enter a very low standby power mode.

The IDT70T651/9 has a RapidWrite Mode which allows the designer

to perform back-to-back write operations without pulsing the R/W input

each cycle. This is especially significant at the 8 and 10ns cycle times of

the IDT70T651/9, easing design considerations at these high perfor-

mance levels.

The 70T633/1 can support an operating voltage of either 3.3V or 2.5V

on one or both ports, controlled by the OPT pins. The power supply for

the core of the device (V

DD

) remains at 2.5V.

2

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3)

70T633/1BC

BC-256

(5,6)

256-Pin BGA

Top View

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

03/13/03

A1

NC

B1

TDI

B2

NC

B3

A

17L

B4

A

14L

B5

A

11L

B6

A

8L

B7

NC

B8

CE

1L

B9

OE

L

B10

INT

L

B11

A

5L

B12

A

2L

B13

A

0L

B14

NC

B15

NC

B16

NC

C1

NC

C2

TDO A

18L

(4)

A

15L

C3

C4

C5

A

12L

C6

A

9L

C7

UB

L

C8

CE

0L

R/W

L

C9

C10

NC

C11

A

4L

C12

A

1L

C13

NC

C14

NC

C15

NC

C16

NC

D1

I/O

9L

D2

V

SS

D3

A

16L

D4

A

13L

D5

A

10L

D6

A

7L

D7

NC

D8

LB

L

D9

SEM

L

BUSY

L

D10

D11

A

6L

D12

A

3L

D13

OPT

L

D14

NC

D15

I/O

8L

D16

NC

E1

I/O

9R

E2

NC

E3

V

DD

V

DDQL

E4

E5

V

DDQL

V

DDQR

V

DDQR

V

DDQL

V

DDQL

V

DDQR

V

DDQR

V

DD

E6

E7

E8

E9

E10

E11

E12

E13

NC

E14

NC

E15

I/O

8R

E16

I/O

10R

I/O

10L

F1

F2

NC

F3

V

DDQL

V

DD

F4

F5

V

DD

F6

V

SS

F7

V

SS

F8

V

SS

F9

V

SS

F10

V

DD

F11

V

DD

V

DDQR

F12

F13

NC

F14

I/O

7L

I/O

7R

F15

F16

I/O

11L

G1

NC

G2

I/O

11R

V

DDQL

V

DD

G3

G4

G5

NC

G6

V

SS

G7

V

SS

G8

V

SS

G9

V

SS

G10

V

SS

G11

V

DD

V

DDQR

I/O

6R

G12

G13

G14

NC

G15

I/O

6L

G16

NC

H1

NC

H2

I/O

12L

V

DDQR

V

SS

H3

H4

H5

V

SS

H6

V

SS

H7

V

SS

H8

V

SS

H9

V

SS

H10

V

SS

H11

V

SS

H12

V

DDQL

I/O

5L

H13

H14

NC

H15

NC

H16

NC

J1

I/O

12R

J2

J3

NC V

DDQR

V

SS

J4

J5

V

SS

J6

V

SS

J7

V

SS

J8

V

SS

J9

V

SS

J10

V

SS

J11

V

SS

J12

V

DDQL

J13

NC

J14

NC

J15

I/O

5R

J16

I/O

13L

I/O

14R

I/O

13R

V

DDQL

ZZ

R

K1

K2

K3

K4

K5

V

SS

K6

V

SS

K7

V

SS

K8

V

SS

K9

V

SS

K10

V

SS

K11

ZZ

L

V

DDQR

I/O

4R

I/O

3R

I/O

4L

K12

K13

K14

K15

K16

NC

L1

NC

L2

I/O

14L

L3

V

DDQL

V

SS

L4

L5

V

SS

L6

V

SS

L7

V

SS

L8

V

SS

L9

V

SS

L10

V

SS

L11

V

SS

L12

V

DDQR

NC

L13

L14

NC

L15

I/O

3L

L16

I/O

15L

M1

NC

M2

I/O

15R

V

DDQR

V

DD

M3

M4

M5

NC

M6

V

SS

M7

V

SS

M8

V

SS

M9

V

SS

M10

V

SS

M11

V

DD

M12

V

DDQL

I/O

2L

M13

M14

NC

M15

I/O

2R

M16

I/O

16R

I/O

16L

N1

N2

NC

N3

V

DDQR

N4

V

DD

N5

V

DD

N6

V

SS

N7

V

SS

N8

V

SS

N9

V

SS

N10

V

DD

N11

V

DD

V

DDQL

I/O

1R

I/O

1L

N12

N13

N14

N15

NC

N16

NC

P1

I/O

17R

P2

NC

P3

V

DD

V

DDQR

V

DDQR

V

DDQL

V

DDQL

V

DDQR

V

DDQR

V

DDQL

V

DDQL

V

DD

P4

P5

P6

P7

P8

P9

P10

P11

P12

P13

NC

P14

I/O

0R

P15

NC

P16

NC

R1

I/O

17L

TMS

R2

R3

A

16R

R4

A

13R

R5

A

10R

R6

A

7R

R7

NC

R8

LB

R

SEM

R

BUSY

R

R9

R10

R11

A

6R

R12

A

3R

R13

NC

R14

NC

R15

I/O

0L

R16

NC

T1

NC

T2

TRST

T3

A

18R

(4)

T4

A

15R

T5

A

12R

T6

A

9R

T7

UB

R

T8

CE

0R

R/W

R

T9

T10

M/S

T11

A

4R

T12

A

1R

T13

OPT

R

T14

NC

T15

NC

T16

,

NC

TCK

NC

A

17R

A

14R

A

11R

A

8R

NC

CE

1R

OE

R

INT

R

A

5R

A

2R

A

0R

NC

5670 drw 02c

NOTES:

1. All V

DD

pins must be connected to 2.5V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

DD

(2.5V), and 2.5V if OPT pin for that port is

set to V

SS

(0V).

3. All V

SS

pins must be connected to ground supply.

4. A

18X

is a NC for IDT70T631.

5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

6. This package code is used to reference the package diagram.

,

3

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Configurations

(1,2,3,8)

(con't.)

03/13/03

V

SS

V

DDQR

V

SS

I/O

9L

I/O

9R

I/O

10L

I/O

10R

I/O

11L

I/O

11R

V

DDQL

V

SS

I/O

12L

I/O

12R

V

DDQR

ZZ

R

V

DD

V

DD

V

SS

V

SS

V

DDQL

V

SS

I/O

13R

I/O

13L

I/O

14R

I/O

14L

V

DDQR

V

SS

I/O

15R

I/O

15L

I/O

16R

I/O

16L

I/O

17R

I/O

17L

V

SS

V

DDQL

NC

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

V

DD

NC

A

18L

(4)

A

17L

A

16L

A

15L

A

14L

A

13L

A

12L

A

11L

A

10L

A

9L

A

8L

A

7L

UB

L

LB

L

CE

1L

CE

0L

V

DD

V

SS

SEM

L

OE

L

R/W

L

BUSY

L

INT

L

NC

A

6L

A

5L

A

4L

A

3L

A

2L

A

1L

A

0L

V

DD

V

SS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

70T633/1DD

DD-144

(5,6,7)

144-Pin TQFP

Top View

(8)

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

OPT

L

V

DDQR

V

SS

I/O

8L

I/O

8R

I/O

7L

I/O

7R

I/O

6L

I/O

6R

V

SS

V

DDQL

I/O

5L

I/O

5R

V

SS

V

DDQR

V

DD

V

DD

V

SS

V

SS

ZZ

L

V

DDQL

I/O

4R

I/O

4L

I/O

3R

I/O

3L

V

SS

V

DDQR

I/O

2R

I/O

2L

I/O

1R

I/O

1L

I/O

0R

I/O

0L

V

SS

V

DDQL

OPT

R

,

V

DD

NC

A

18R

(4)

A

17R

A

16R

A

15R

A

14R

A

13R

A

12R

A

11R

A

10R

A

9R

A

8R

A

7R

UB

R

LB

R

CE

1R

CE

0R

V

DD

V

SS

SEM

R

OE

R

R/W

R

BUSY

R

INT

R

M/S

A

6R

A

5R

A

4R

A

3R

A

2R

A

1R

A

0R

V

DD

V

SS

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

5670 drw 02a

NOTES:

1. All V

DD

pins must be connected to 2.5V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

DD

(2.5V), and 2.5V if OPT pin for that port is

set to V

SS

(0V).

3. All V

SS

pins must be connected to ground.

4. A

18X

is a NC for IDT70T631.

5. Package body is approximately 20mm x 20mm x 1.4mm.

6. This package code is used to reference the package diagram.

7. 8ns Commercial and 10ns Industrial speed grades are not available in the DD-144 package.

8. This text does not indicate orientation of the actual part-marking.

9. Due to the restricted number of pins, JTAG is not supported in the DD-144 package.

4

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Configurations

(1,2,3)

(con't.)

03/12/03

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

I/O

9L

2

NC

3

V

S S

4

TDO

5

NC

6

A

16L

7

A

12L

8

A

8L

9

NC

10 11

V

DD

12

INT

L

13 14

A

4L

A

0L

15

OPT

L

16 17

NC

V

SS

SEM

L

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

NC

V

S S

NC

TDI

A

17L

A

13L

A

9L

NC

CE

0L

V

SS

BUSY

L

A

5L

A

1L

V

S S

V

DD QR

I/O

8L

NC

V

DD QL

I/O

9R

V

DDQR

V

DD

A

18L

(4 )

A

14 L

A

1 0L

UB

L

CE

1L

V

SS

R/

W

L

A

6L

A

2L

V

DD

I/O

8R

NC

V

SS

NC

V

SS

I/O

10L

NC

A

15 L

A

11L

A

7 L

LB

L

V

DD

OE

L

NC

A

3L

V

DD

NC

V

D DQL

I/O

7L

I/O

7 R

I/O

11L

NC

V

D DQ R

I/O

10 R

I/O

6L

NC

V

SS

NC

V

DD QL

I/O

11R

NC

V

SS

V

S S

I/O

6R

NC

V

D DQ R

NC

V

S S

I/O

12L

NC

V

DD QL

I/O

5L

NC

V

DD

NC

V

D DQ R

I/O

12R

70T633/1BF

BF-208

(5,6)

208-Ball BGA

Top View

(7)

V

D D

NC

V

SS

I/O

5R

V

DD QL

V

D D

V

SS

ZZ

R

ZZ

L

V

DD

V

SS

V

DDQ R

I/O

14R

V

S S

I/O

13R

V

S S

I/O

3R

V

D DQL

I/O

4R

V

SS

NC

I/O

14L

V

D DQ R

I/O

13L

NC

I/O

3L

V

SS

I/O

4L

V

DD QL

NC

I/O

15R

V

SS

V

S S

NC

I/O

2R

V

DDQ R

NC

V

S S

NC

I/O

15 L

I/O

1R

V

DD QL

NC

I/O

2L

I/O

16R

I/O

16L

V

D DQ R

NC

TRST

A

16R

A

12R

A

8R

NC

V

D D

SEM

R

INT

R

A

4R

NC

I/O

1L

V

SS

NC

V

S S

NC

I/O

17 R

TCK

A

17R

A

13R

A

9R

NC

CE

0R

V

S S

BUSY

R

R/

W

R

A

5R

A

1R

V

S S

V

D DQ L

I/O

0R

V

DDQR

NC

I/O

17L

V

D DQ L

TMS

A

18R

(4)

A

14R

A

1 0R

UB

R

CE

1R

V

S S

A

6R

A

2R

V

S S

NC

V

SS

NC

V

S S

NC

V

DD

NC

A

15R

A

11R

A

7R

LB

R

V

DD

OE

R

M/

S

A

3R

A

0R

V

DD

OPT

R

NC

I/O

0L

5670 drw 02b

NOTES:

1. All V

DD

pins must be connected to 2.5V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

DD

(2.5V), and 2.5V if OPT pin for that port is

set to V

SS

(0V).

3. All V

SS

pins must be connected to ground.

4. A

18X

is a NC for IDT70T631.

5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

6. This package code is used to reference the package diagram.

7. This text does not indicate orientation of the actual part-marking.

5

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	IDT (Integrated Device Technology)
零件包装代码	QFP
包装说明	LFQFP, QFP144,.87SQ,20
针数	144
Reach Compliance Code	compliant
ECCN代码	3A991.B.2.A
最长访问时间	15 ns
I/O 类型	COMMON
JESD-30 代码	S-PQFP-G144
JESD-609代码	e3
长度	20 mm
内存密度	9437184 bit
内存集成电路类型	DUAL-PORT SRAM
内存宽度	18
功能数量	1
端口数量	2
端子数量	144
字数	524288 words
字数代码	512000
工作模式	ASYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	512KX18
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	LFQFP
封装等效代码	QFP144,.87SQ,20
封装形状	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行	PARALLEL
峰值回流温度（摄氏度）	260
电源	2.5,2.5/3.3 V
认证状态	Not Qualified
座面最大高度	1.6 mm
最大待机电流	0.01 A
最小待机电流	2.4 V
最大压摆率	0.305 mA
最大供电电压 (Vsup)	2.6 V
最小供电电压 (Vsup)	2.4 V
标称供电电压 (Vsup)	2.5 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Matte Tin (Sn)
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	30
宽度	20 mm
Base Number Matches	1

	70T633S15DDG	70T633S12DDG	70T633S12DDGI	70T631S12DDGI	70T631S15DDG	70T631S12DDG
描述	Dual-Port SRAM, 512KX18, 15ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HIEGHT, GREEN, TQFP-144	Dual-Port SRAM, 512KX18, 12ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HIEGHT, GREEN, TQFP-144	Dual-Port SRAM, 512KX18, 12ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HIEGHT, GREEN, TQFP-144	Dual-Port SRAM, 256KX18, 12ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HIEGHT, GREEN, TQFP-144	Dual-Port SRAM, 256KX18, 15ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HIEGHT, GREEN, TQFP-144	Dual-Port SRAM, 256KX18, 12ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HIEGHT, GREEN, TQFP-144
是否无铅	不含铅	不含铅	不含铅	不含铅	不含铅	不含铅
是否Rohs认证	符合	符合	符合	符合	符合	符合
零件包装代码	QFP	QFP	QFP	QFP	QFP	QFP
包装说明	LFQFP, QFP144,.87SQ,20	LFQFP, QFP144,.87SQ,20	LFQFP, QFP144,.87SQ,20	LFQFP, QFP144,.87SQ,20	LFQFP, QFP144,.87SQ,20	LFQFP, QFP144,.87SQ,20
针数	144	144	144	144	144	144
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
ECCN代码	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
最长访问时间	15 ns	12 ns	12 ns	12 ns	15 ns	12 ns
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	S-PQFP-G144	S-PQFP-G144	S-PQFP-G144	S-PQFP-G144	S-PQFP-G144	S-PQFP-G144
JESD-609代码	e3	e3	e3	e3	e3	e3
长度	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm
内存密度	9437184 bit	9437184 bit	9437184 bit	4718592 bit	4718592 bit	4718592 bit
内存集成电路类型	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM
内存宽度	18	18	18	18	18	18
功能数量	1	1	1	1	1	1
端口数量	2	2	2	2	2	2
端子数量	144	144	144	144	144	144
字数	524288 words	524288 words	524288 words	262144 words	262144 words	262144 words
字数代码	512000	512000	512000	256000	256000	256000
工作模式	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
最高工作温度	70 °C	70 °C	85 °C	85 °C	70 °C	70 °C
组织	512KX18	512KX18	512KX18	256KX18	256KX18	256KX18
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LFQFP	LFQFP	LFQFP	LFQFP	LFQFP	LFQFP
封装等效代码	QFP144,.87SQ,20	QFP144,.87SQ,20	QFP144,.87SQ,20	QFP144,.87SQ,20	QFP144,.87SQ,20	QFP144,.87SQ,20
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	260	260	260	260	260	260
电源	2.5,2.5/3.3 V	2.5,2.5/3.3 V	2.5,2.5/3.3 V	2.5,2.5/3.3 V	2.5,2.5/3.3 V	2.5,2.5/3.3 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm
最大待机电流	0.01 A	0.01 A	0.02 A	0.02 A	0.01 A	0.01 A
最小待机电流	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V
最大压摆率	0.305 mA	0.355 mA	0.395 mA	0.395 mA	0.305 mA	0.355 mA
最大供电电压 (Vsup)	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V
最小供电电压 (Vsup)	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V
标称供电电压 (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
表面贴装	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
端子面层	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
端子位置	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
处于峰值回流温度下的最长时间	30	30	30	30	30	30
宽度	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm
Base Number Matches	1	1	1	1	1	1
厂商名称	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	-	IDT (Integrated Device Technology)

70T633S15DDG

70T633S15DDG概述

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