Micrel, Inc.
3.3V/5V 2.5GHz PROGRAMMABLE
DELAY WITH FINE TUNE CONTROL
ECL Pro®
SY100EP196V
ECL Pro®
SY100EP196V
FEATURES
■
Pin-for-pin, plug-in compatible to the ON
Semiconductor MC100EP196
■
Maximum frequency > 2.5GHz
■
Programmable range: 2.2ns to 12.2ns
■
10ps increments
■
30ps fine tuning range
■
PECL mode operating range: V
CC
= 3.0V to 5.5V
with V
EE
= 0V
■
NECL mode operating range: V
CC
= 0V
with V
EE
= –3.0V to –5.5V
■
Open input default state
■
■
■
■
■
Safety clamp on inputs
A logic high on the /EN pin will force Q to logic low
D[0:10] can accept either ECL, CMOS, or TTL inputs
V
BB
output reference voltage
Available in a 32-pin TQFP package
ECL Pro®
DESCRIPTION
The SY100EP196V is a programmable delay line, varying
the time a logic signal takes to traverse from IN to Q. This
delay can vary from about 2.2ns to about 12.2ns. The input
can be PECL, LVPECL, NECL, or LVNECL.
The delay varies in discrete steps based on a control
word presented to SY100EP196V. The 10-bit width of this
latched control register allows for delay increments of
approximately 10ps. In addition, delay may be varied
continuously in about a 30ps range by setting the voltage at
the FTUNE pin.
An eleventh control bit allows the cascading of multiple
SY100EP196V devices, for a wider delay range. Each
additional SY100EP196V effectively doubles the delay range
available.
For maximum flexibility, the control register interface
accepts CMOS or TTL level signals, as well as the input
level at the IN± pins.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
APPLICATIONS
■
Clock de-skewing
■
Timing adjustment
■
Aperture centering
CROSS REFERENCE TABLE
Micrel Semiconductor
SY100EP196VTI
SY100EP196VTITR
ON Semiconductor
MC100EP196FA
MC100EP196FAR2
TYPICAL APPLICATIONS CIRCUIT
TYPICAL PERFORMANCE
Delay vs. Tap
Data Signal
of Unknown Phase
SY100EP196V
CLOCK+
CLOCK–
Fine Tune Voltage
IN
/IN
FTUNE /Q
D[9:0]
Q
12000
D
CK
Q+
Flip-Flop
DELAY (ps)
Q–
10000
8000
6000
4000
2000
CONTROL
LOGIC
0
0
200 400 600 800 1000 1200
TAP (DIGITAL WORD)
ECL Pro is a registered trademark of Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
Rev.: D
Amendment: /0
1
Issue Date: December 2005
Micrel, Inc.
ECL Pro®
SY100EP196V
PACKAGE/ORDERING INFORMATION
D7
D6
D5
D4
VEE
D3
D2
D1
Ordering Information
(1)
24
23
22
21
20
19
18
17
VEE
D0
VCC
Q
/Q
VCC
VCC
FTUNE
32 31 30 29 28 27 26 25
D8
D9
D10
IN
/IN
VBB
VEF
VCF
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
VEE
LEN
SETMIN
SETMAX
VCC
/CASCADE
CASCADE
/EN
Part Number
SY100EP196VTI
SY100EP196VTITR
(2)
SY100EP196VTG
(3)
SY100EP196VTGTR
(2, 3)
Package
Type
T32-1
T32-1
T32-1
T32-1
Operating
Range
Industrial
Industrial
Industrial
Industrial
Package
Marking
SY100EP196V
SY100EP196V
SY100EP196V with
Pb-Free bar-line indicator
SY100EP196V with
Pb-Free bar-line indicator
Lead
Finish
Sn-Pb
Sn-Pb
Pb-Free
NiPdAu
Pb-Free
NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
32-Pin TQFP (T32-1)
FUNCTIONAL BLOCK DIAGRAM
IN
/IN
/EN
512
GD
0
1
0
0
0
0
256
GD
1
128
GD
1
64
GD
1
32
GD
1
0
0
0
0
0
16
GD
1
8
GD
1
4
GD
1
2
GD
1
1
GD
1
FTUNE
D[9:0]
LEN
SETMIN
SETMAX
10-bit
Latch
1
GD
0
1
Q
/Q
D[10]
Latch
CASCADE
/CASCADE
V
BB
V
CF
V
EF
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
ECL Pro®
SY100EP196V
PIN DESCRIPTION
Pin Number
23, 25, 26, 27, 29,
30, 31, 32, 1, 2
Pin Name
D[0:9]
Pin Function
CMOS, ECL, or TTL Select Inputs: These digital control signals adjust the amount of
delay from IN to Q. Please refer to the “AC Electrical Table” (page 3) and Table 7 (page
17) for delay values. Figure 9 shows how to interface these inputs to various logic family
standards. These inputs default to logic low when left unconnected. Bit 0 is the least
significant bit, and bit 9 is the most significant bit.
CMOS, ECL, or TTL Select Input: This input latches just like D[0:9] does. It drives the
CASCADE, /CASCADE differential pair. Use only when cascading two or more
SY100EP196V to extend the range of delays required.
ECL Input: This is the signal to be delayed. If this input pair is left unconnected, this is
equivalent to a logic low input.
Voltage Output Reference: When using a single-ended logic source for IN and /IN,
connect the unused input of the differential pair to this pin. This pin can also re-bias AC-
coupled inputs to IN and /IN. When used, de-couple this pin to V
CC
through an 0.01µF
capacitor. Limit current sinking or sourcing to 0.5mA or less.
Voltage Output: Connect this pin to VCF when the D inputs are ECL. Refer to the
“Digital
Control Logic Standard”
section of the
“Functional Description”
to interface the D inputs to
CMOS or TTL.
Voltage Input: The voltage at this pin sets the logic transition threshold for the D inputs.
Most Negative Supply. Supply ground for PECL systems.
ECL Control Input: When logic low, the D inputs flow through. Any changes to the D inputs
reflect in the delay between IN, /IN and Q, /Q. When logic high, the logic values at D are
latched, and these latched bits determine the delay.
ECL Control Input: When logic high, the contents of the D register are reset. This sets the
delay to the minimum possible, equivalent to D[0:9] being set to 0000000000. When logic
low, the value of the D register, or the logic value of SETMAX determines the delay from
IN, /IN to Q, /Q. This input defaults to logic low when left unconnected.
ECL Control Input: When logic high and SETMIN is logic low, the contents of the D
register are set high, and the delay is set to one step greater than the maximum possible
with D[0:9] set to 1111111111. When logic low, the value of the D register, or the logic
value of SETMIN determines the delay from IN, /IN to Q, /Q. This input defaults to logic
low when left unconnected.
Most Positive Supply: Supply ground for NECL systems. Bypass to V
EE
with 0.1µF and
0.01µF low ESR capacitors.
100k ECL Outputs: These outputs are used when cascading two or more SY100EP196V
to /CASCADE extend the delay range required. Refer to Table 7 (page 17) for delay
values.
ECL Control Input: When set active low, Q, /Q are a delayed version of IN, /IN. When set
inactive high, IN, /IN are gated such that Q, /Q become a differential logic low. This input
defaults to logic low when left unconnected.
Voltage Control Input: By varying the voltage at this pin from V
CC
through V
EE
, the delay
may be fine tuned by approximately
±15ps.
100k ECL Outputs: This signal pair is the delayed version of IN, /IN.
3
D[10]
4, 5
6
IN, /IN
VBB
7
VEF
8
9, 24, 28
10
VCF
VEE
LEN
11
SETMIN
12
SETMAX
13, 18, 19, 22
14, 15
VCC
CASCADE,
16
/EN
17
20, 21
FTUNE
Q, /Q
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
ECL Pro®
SY100EP196V
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
)
PECL Mode (V
EE
=0V) ............................. –0.5V to +6.0V
Supply Voltage (V
EE
)
NECL Mode (V
CC
=0V) ............................ +0.5V to –6.0V
Any Input Voltage (V
IN
)
PECL Mode ....................................... –0.5V to V
CC
+0.5V
NECL Mode ....................................... +0.5V to V
EE
–0.5V
ECL Output Current (I
OUT
)
Continuous ............................................................. 50mA
Surge .................................................................... 100mA
I
BB
Sink/Source Current ..........................................
±0.5mA
Lead Temperature (soldering, 20 sec.) ................... +260°C
Storage Temperature (T
S
) ....................... –65°C to +150°C
ESD Rating
(3)
........................................................... >1.5kV
Operating Ratings
(2)
Supply Voltage (V
CC
)
PECL Mode (V
EE
=0V) ............................. +3.0V to +5.5V
Supply Voltage (V
EE
)
NECL Mode (V
CC
=0V) ............................ –3.0V to –5.5V
Ambient Temperature (T
A
) ......................... –40°C to +85°C
Package Thermal Resistance
TQFP-32 (θ
JA
)
Still-air ............................................................. 50°C/W
500lfpm ............................................................ 42°C/W
TQFP-32 (θ
JC
) ..................................................... 20°C/W
DC ELECTRICAL CHARACTERISTICS
T
A
= –40°C to +85°C
Symbol
V
CC
V
EE
I
EE
Notes:
1. Permanent device damage may occur if
“Absolute Maximum Ratings”
are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to
“Absolute Maximum Rating”
conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Devices are ESD sensitive. Handling precautions recommended.
4. Required 500lfpm air flow when using +5V or –5V power supply.
Parameter
Power Supply Voltage (PECL)
Power Supply Voltage (NECL)
Power Supply Current
(4)
Condition
Min
3.0
4.5
–3.6
–5.5
Typ
3.3
5.0
–3.3
–5.0
150
Max
3.6
5.5
–3.0
–4.5
175
Units
V
V
V
V
mA
No Load, Over Supply Voltage
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
ECL Pro®
SY100EP196V
(100kEP) LVPECL DC ELECTRICAL CHARACTERISTICS
V
CC
= 3.3V, V
EE
= 0V; T
A
= –40°C to +85°C
(5, 6)
Symbol
V
OH
V
OL
V
IH
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
PECL
CMOS
TTL
Input LOW Voltage
PECL
CMOS
TTL
Output Voltage Reference
Input Select Voltage
Mode Connection
Input HIGH Voltage Common
Mode Range
(7)
Input HIGH Current
Input LOW Current
IN
/IN
0.5
–150
Figure 5
Condition
Figures 2, 3, 6
Figures 2, 3, 6
Figures 1, 4
2075
1815
2000
Figures 1, 4
1355
1675
1485
800
1875
1720
2000
1975
1825
2100
3.3
150
mV
mV
mV
mV
mV
mV
V
µA
µA
µA
2420
mV
mV
mV
Min
2155
1355
Typ
2280
1480
Max
2405
1605
Units
mV
mV
V
IL
V
BB
V
CF
V
EF
V
IHCMR
I
IH
I
IL
1775
1610
1900
2.0
Notes:
5. Device is guaranteed to meet the DC specifications, shown in the table above, after thermal equilibrium has been established. The device is tested in
a socket such that transverse airflow of
≥
500lfpm is maintained.
6. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.3V to –2.2V.
7. V
IHCMR
maximum varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input signal.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
