NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX6SDLCEC
Rev. 8, 09/2017
i.MX 6Solo/6DualLite
Applications Processors
for Consumer Products
MCIMX6SxExxxxxB
MCIMX6SxExxxxxC
MCIMX6SxExxxxxD
MCIMX6UxExxxxxB
MCIMX6UxExxxxxC
MCIMX6UxExxxxxD
MCIMX6SxDxxxxxB
MCIMX6SxDxxxxxC
MCIMX6SxDxxxxxD
MCIMX6UxDxxxxxB
MCIMX6UxDxxxxxC
MCIMX6UxDxxxxxD
Package Information
Plastic Package
BGA Case 2240 21 x 21 mm, 0.8 mm pitch
Ordering Information
See
Table 1 on page 3
1
Introduction
1
The i.MX 6Solo/6DualLite processors represent the
latest achievement in integrated multimedia-focused
products offering high performance processing with
lower cost, as well as optimization for low power
consumption.
The processors feature advanced implementation of
single/dual ARM
®
Cortex
®
-A9 core, which operates at
speeds of up to 1 GHz. They include 2D and 3D graphics
processors, 1080p video processing, and integrated
power management. Each processor provides a 32/64-bit
DDR3/DDR3L/LPDDR2-800 memory interface and a
number of other interfaces for connecting peripherals,
such as WLAN, Bluetooth
®
, GPS, hard drive, displays,
and camera sensors.
The i.MX 6Solo/6DualLite processors are specifically
useful for applications such as:
• Web and multimedia tablets
• Web and multimedia tablets
2
3
4
5
6
7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3 Updated Signal Naming Convention . . . . . . . . . . . .9
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1 Special Signal Considerations . . . . . . . . . . . . . . . .21
3.2 Recommended Connections for Unused Analog
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .23
4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . .23
4.2 Power Supplies Requirements and Restrictions. . .33
4.3 Integrated LDO Voltage Regulator Parameters . . .34
4.4 PLL’s Electrical Characteristics. . . . . . . . . . . . . . . .37
4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . .38
4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .39
4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .45
4.8 Output Buffer Impedance Parameters . . . . . . . . . .49
4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . .52
4.10 General-Purpose Media Interface (GPMI) Timing .64
4.11 External Peripheral Interface Parameters. . . . . . . .72
Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . .134
5.1 Boot Mode Configuration Pins . . . . . . . . . . . . . . .134
5.2 Boot Device Interface Allocation. . . . . . . . . . . . . .135
Package Information and Contact Assignments . . . . . .136
6.1 Updated Signal Naming Convention . . . . . . . . . .136
6.2 21x21 mm Package Information . . . . . . . . . . . . . .137
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
© 2012-2017 NXP B.V.
Introduction
•
•
•
•
•
•
Color eReaders
IPTV
Human Machine Interfaces (HMI)
Portable medical
IP phones
Home energy management systems
The i.MX 6Solo/6DualLite applications processors feature:
• Applications processors—The processors enhance the capabilities of high-tier portable
applications by fulfilling the ever increasing MIPS requirements of operating systems and games.
The Dynamic Voltage and Frequency Scaling (DVFS) provides significant power reduction,
allowing the device to run at lower voltage and frequency with sufficient MIPS for tasks, such as
audio decode.
• Multilevel memory system—The multilevel memory system of each processor is based on the L1
instruction and data caches, L2 cache, and internal and external memory. The processors support
many types of external memory devices, including DDR3, DDR3L, LPDDR2, NOR Flash,
PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed NAND,
including eMMC up to rev 4.4/4.41.
• Smart speed technology—The processors have power management throughout the IC that enables
the rich suite of multimedia features and peripherals to consume minimum power in both active
and various low power modes. Smart speed technology enables the designer to deliver a
feature-rich product, requiring levels of power far lower than industry expectations.
• Dynamic voltage and frequency scaling—The processors improve the power efficiency of devices
by scaling the voltage and frequency to optimize performance.
• Multimedia powerhouse—The multimedia performance of each processor is enhanced by a
multilevel cache system, NEON™ MPE (Media Processor Engine) co-processor, a multi-standard
hardware video codec, an image processing unit (IPU), a programmable smart DMA (SDMA)
controller, and an asynchronous sample rate converter.
• Powerful graphics acceleration—Each processor provides two independent, integrated graphics
processing units: an OpenGL
®
ES 2.0 3D graphics accelerator with a shader and a 2D graphics
accelerator.
• Interface flexibility—Each processor supports connections to a variety of interfaces: LCD
controller for up to two displays (including parallel display, HDMI1.4, MIPI display, and LVDS
display), dual CMOS sensor interface (parallel or through MIPI), high-speed USB on-the-go with
PHY, high-speed USB host with PHY, multiple expansion card ports (high-speed MMC/SDIO host
and other), 10/100/1000 Mbps Gigabit Ethernet controller two CAN ports, ESAI audio interface,
and a variety of other popular interfaces (such as UART, I
2
C, and I
2
S serial audio, and PCIe-II).
• Eink Panel Display Controller—The processors integrate EPD controller that supports E-INK
color and monochrome with up to 1650x2332 resolution and 5-bit grayscale (32-levels per color
channel).
• Advanced security—The processors deliver hardware-enabled security features that enable secure
e-commerce, digital rights management (DRM), information encryption, secure boot, and secure
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 8, 09/2017
2
NXP Semiconductors
Introduction
•
software downloads. The security features are discussed in detail in the
i.MX 6Solo/6DualLite
Security Reference Manual
(IMX6DQ6SDLSRM).
Integrated power management—The processors integrate linear regulators and internally generate
voltage levels for different domains. This significantly simplifies system power management
structure.
1.1
Ordering Information
Table 1
provides examples of orderable part numbers covered by this data sheet.
Table 1
does not include
all possible orderable part numbers. The latest part numbers are available on the web page
nxp.com/imx6series. If the desired part number is not listed in
Table 1,
go to
nxp.com/imx6series
or
contact a NXP representative for details.
Table 1. Example Orderable Part Numbers
Part Number
i.MX6 CPU
Solo/
DualLite
Options
Speed
Grade
1
1 GHz
1 GHz
1 GHz
1 GHz
1 GHz
1 GHz
1 GHz
Temperature
Grade
Package
MCIMX6U8DVM10AB DualLite With VPU, GPU, EPDC, MLB
2x ARM Cortex-A9 64-bit DDR
MCIMX6U8DVM10AC DualLite With VPU, GPU, EPDC, MLB
2x ARM Cortex-A9 64-bit DDR
MCIMX6U8DVM10AD DualLite With VPU, GPU, EPDC, MLB
2x ARM Cortex-A9 64-bit DDR
MCIMX6U5DVM10AB DualLite With VPU, GPU, MLB, no EPDC
2x ARM Cortex-A9 64-bit DDR
MCIMX6U5DVM10AC DualLite With VPU, GPU, MLB, no EPDC
2x ARM Cortex-A9 64-bit DDR
MCIMX6U5DVM10AD DualLite With VPU, GPU, MLB, no EPDC
2x ARM Cortex-A9 64-bit DDR
SCIMX6U5DVM10CB
DualLite HDCP enabled with VPU, GPU, MLB, no
EPDC
2x ARM Cortex-A9 64-bit DDR
DualLite HDCP enabled with VPU, GPU, MLB, no
EPDC
2x ARM Cortex-A9 64-bit DDR
DualLite HDCP enabled with VPU, GPU, MLB, no
EPDC
2x ARM Cortex-A9 64-bit DDR
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm, 0.8 mm
pitch, MAPBGA
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm, 0.8 mm
pitch, MAPBGA
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm, 0.8 mm
pitch, MAPBGA
Extended 21 mm x 21 mm,
Commercial 0.8 mm pitch, MAPBGA
Extended 21 mm x 21 mm,
Commercial 0.8 mm pitch, MAPBGA
Extended 21 mm x 21 mm, 0.8 mm
Commercial pitch, MAPBGA
SCIMX6U5DVM10CC
1 GHz
SCIMX6U5DVM10CD
1 GHz
MCIMX6U5EVM10AB DualLite With VPU, GPU, MLB, no EPDC
2x ARM Cortex-A9 64-bit DDR
MCIMX6U5EVM10AC DualLite With VPU, GPU, MLB, no EPDC
2x ARM Cortex-A9 64-bit DDR
MCIMX6U5EVM10AD DualLite With VPU, GPU, MLB, no EPDC
2x ARM Cortex-A9 64-bit DDR
1 GHz
1 GHz
1 GHz
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 8, 09/2017
NXP Semiconductors
3
Introduction
Table 1. Example Orderable Part Numbers (continued)
Part Number
MCIMX6S8DVM10AB
MCIMX6S8DVM10AC
MCIMX6S8DVM10AD
MCIMX6S5DVM10AB
MCIMX6S5DVM10AC
MCIMX6S5DVM10AD
SCIMX6S5DVM10CB
i.MX6 CPU
Solo/
DualLite
Options
With VPU, GPU, MLB, EPDC
1x ARM Cortex-A9 32-bit DDR
With VPU, GPU, MLB, EPDC
1x ARM Cortex-A9 32-bit DDR
With VPU, GPU, MLB, EPDC
1x ARM Cortex-A9 32-bit DDR
With VPU, GPU, MLB, no EPDC
1x ARM Cortex-A9 32-bit DDR
With VPU, GPU, MLB, no EPDC
1x ARM Cortex-A9 32-bit DDR
With VPU, GPU, MLB, no EPDC
1x ARM Cortex-A9 32-bit DDR
HDCP enabled with VPU, GPU, MLB, no
EPDC
1x ARM Cortex-A9 32-bit DDR
HDCP enabled with VPU, GPU, MLB, no
EPDC
1x ARM Cortex-A9 32-bit DDR
HDCP enabled with VPU, GPU, MLB, no
EPDC
1x ARM Cortex-A9 32-bit DDR
With VPU, GPU, MLB, no EPDC
1x ARM Cortex-A9 32-bit DDR
With VPU, GPU, MLB, no EPDC
1x ARM Cortex-A9 32-bit DDR
With VPU, GPU, MLB, no EPDC
1x ARM Cortex-A9 32-bit DDR
Speed
Grade
1
1 GHz
1 GHz
1 GHz
1 GHz
1 GHz
1 GHz
1 GHz
Temperature
Grade
Package
Solo
Solo
Solo
Solo
Solo
Solo
Solo
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm, 0.8 mm
pitch, MAPBGA
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm, 0.8 mm
pitch, MAPBGA
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm,
0.8 mm pitch, MAPBGA
Commercial 21 mm x 21 mm, 0.8 mm
pitch, MAPBGA
Extended 21 mm x 21 mm,
Commercial 0.8 mm pitch, MAPBGA
Extended 21 mm x 21 mm,
Commercial 0.8 mm pitch, MAPBGA
Extended 21 mm x 21 mm, 0.8 mm
Commercial pitch, MAPBGA
SCIMX6S5DVM10CC
Solo
1 GHz
SCIMX6S5DVM10CD
Solo
1 GHz
MCIMX6S5EVM10AB
MCIMX6S5EVM10AC
MCIMX6S5EVM10AD
1
Solo
Solo
Solo
1 GHz
1 GHz
1 GHz
If a 24 MHz input clock is used (required for USB), then the maximum SoC speed is limited to 996 MHz.
Figure 1
describes the part number nomenclature to identify the characteristics of a specific part number
(for example, cores, frequency, temperature grade, fuse options, and silicon revision).
The primary characteristic that differentiates which data sheet applies to a specific part is the temperature
grade (junction) field. The following list describes the correct data sheet to use for a specific part:
• The
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors
data sheet
(IMX6SDLAEC) covers parts listed with an “A (Automotive temp)”
• The
i.MX 6Solo/6DualLite Applications Processors for Consumer Products
data sheet
(IMX6SDLCEC) covers parts listed with a “D (Commercial temp)” or “E (Extended Commercial
temp)”
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 8, 09/2017
4
NXP Semiconductors
Introduction
•
The
i.MX 6Solo/6DualLite Applications Processors for Industrial Products
data sheet
(IMX6SDLIEC) covers parts listed with “C (Industrial temp)”
For more information go to
nxp.com/imx6series
or contact a NXP representative for details.
MC
IMX6
X
@
+
VV
$$
%
A
Silicon revision
1
Rev 1.1
Qualification level
Prototype Samples
Mass Production
Special
MC
PC
MC
SC
A
B
C
D
Rev 1.2 (Maskset ID: 2N81E)
Rev 1.3 (Maskset ID: 3N81E)
Rev 1.4 (Maskset ID: 4N81E)
Fusing
Part # series
i.MX 6DualLite
2x ARM Cortex-A9, 64-bit DDR
i.MX 6Solo
1x ARM Cortex-A9, 32-bit DDR
X
U
S
Default settings
HDCP enabled
%
A
C
Frequency
800 MHz
2
1 GHz
3
$$
08
10
RoHS
Part differentiator
Consumer
Industrial
Automotive
Consumer
Automotive
Automotive
VPU
VPU
VPU
VPU
–
–
GPU
GPU
GPU
GPU
GPU
–
EPDC
–
–
–
–
–
MLB
–
MLB
MLB
MLB
MLB
@
8
7
6
5
4
1
Package type
Temperature Tj
Commercial: 0 to + 95
°
C
Extended commercial: -20 to + 105
°
C
Industrial: -40 to +105
°
C
Automotive: -40 to + 125
°
C
+
D
E
C
A
MAPBGA 21 x 21 0.8mm
VM
1. See the nxp.com\imx6series Web page for latest information on the available silicon revision.
2. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz.
3. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz.
Figure 1. Part Number Nomenclature—i.MX 6Solo and 6DualLite
Figure 2. Example Part Marking
1.2
Features
The i.MX 6Solo/6DualLite processors are based on ARM Cortex-A9 MPCore Platform, which has the
following features:
• The i.MX 6Solo supports single ARM Cortex-A9 MPCore (with TrustZone)
• The i.MX 6DualLite supports dual ARM Cortex-A9 MPCore (with TrustZone)
• The core configuration is symmetric, where each core includes:
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 8, 09/2017
NXP Semiconductors
5
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