Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
FEATURES
•
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
•
Balanced propagation delays
•
All inputs have Schmitt-trigger
actions
•
Inputs accepts voltages higher than
V
CC
•
For AHC only:
operates with CMOS input levels
•
For AHCT only:
operates with TTL input levels
•
Specified from
−40
to +85 and +125
°C.
DESCRIPTION
The 74AHC/AHCT125 are
high-speed Si-gate CMOS devices
and are pin compatible with low
power Schottky TTL (LSTTL). They
are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT125 are four
non-inverting buffer/line drivers with
3-state outputs. The 3-state outputs
(nY) are controlled by the output
enable input (nOE). A HIGH at n
causes the outputs to assume a
HIGH-impedance OFF-state.
The ‘125’ is identical to the ‘126’ but
has active LOW enable inputs.
74AHC125; 74AHCT125
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
3.0 ns.
TYPICAL
SYMBOL
t
PHL
/t
PLH
C
I
C
O
C
PD
PARAMETER
propagation delay
nA to nY
input capacitance
output capacitance
power dissipation
capacitance
C
L
= 50 pF;
f = 1 MHz;
notes 1 and 2
CONDITIONS
AHC
C
L
= 15 pF;
V
CC
= 5 V
V
I
= V
CC
or GND
3.0
3.0
4.0
10
AHCT
3.0
3.0
4.0
12
ns
pF
pF
pF
UNIT
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
FUNCTION TABLE
See note 1.
INPUT
nOE
L
L
H
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
nA
L
H
X
OUTPUT
nY
L
H
Z
1999 Sep 27
2
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
RECOMMENDED OPERATING CONDITIONS
74AHC125; 74AHCT125
74AHC
SYMBOL
V
CC
V
I
V
O
T
amb
PARAMETER
DC supply voltage
input voltage
output voltage
operating ambient temperature
range
see DC and AC
characteristics per
device
V
CC
= 5 V
±0.5
V
CONDITIONS
MIN.
2.0
0
0
−40
−40
TYP. MAX. MIN.
5.0
−
−
+25
+25
−
−
5.5
5.5
V
CC
+85
4.5
0
0
−40
74AHCT
UNIT
TYP. MAX.
5.0
−
−
+25
+25
−
−
5.5
5.5
V
CC
+85
V
V
V
°C
+125
−40
100
20
−
−
+125
°C
−
20
ns/V
t
r
,t
f
(∆t/∆f) input rise and fall rates
V
CC
= 3.3 V
±0.3
V
−
−
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
V
I
I
IK
I
OK
I
O
I
CC
T
stg
P
D
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70
°C
the value of P
D
derates linearly with 8 mW/K.
For TSSOP packages: above 60
°C
the value of P
D
derates linearly with 5.5 mW/K.
PARAMETER
DC supply voltage
input voltage range
DC input diode current
DC output diode current
DC V
CC
or GND current
storage temperature range
power dissipation per package
for temperature range:
−40
to +125
°C;
note 2
V
I
<
−0.5
V; note 1
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V; note 1
CONDITIONS
MIN. MAX. UNIT
−0.5
−0.5
−
−
−
−
−65
−
+7.0
+7.0
−20
±20
±25
±75
500
V
V
mA
mA
mA
mA
mW
DC output source or sink current
−0.5
V < V
O
< V
CC
+ 0.5 V
+150
°C
1999 Sep 27
5
FPGA/CPLD
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