PD - 97771
IRFS4510PbF
IRFSL4510PbF
HEXFET
®
Power MOSFET
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
Benefits
l
Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
D
G
S
V
DSS
R
DS(on)
typ.
max.
I
D (Silicon Limited)
D
100V
11.3mΩ
13.9mΩ
61A
D
G
D
S
G
D
S
D
2
Pak
IRFS4510PbF
G
D
TO-262
IRFSL4510PbF
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
C
= 25°C
V
GS
dv/dt
T
J
T
STG
Parameter
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Max.
61
43
250
140
0.95
± 20
3.2
-55 to + 175
300
10lb in (1.1N m)
130
See Fig. 14, 15, 22a, 22b,
Units
A
W
W/°C
V
V/ns
°C
c
e
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
x
x
Avalanche Characteristics
E
AS (Thermally limited)
I
AR
E
AR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
d
mJ
A
mJ
f
Thermal Resistance
R
θJC
R
θJA
Junction-to-Case
Junction-to-Ambient
i
Parameter
Typ.
–––
–––
Max.
1.05
40
Units
°C/W
ij
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1
4/10/12
IRFS/SL4510PbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
ΔV
(BR)DSS
/ΔT
J
R
DS(on)
V
GS(th)
I
DSS
I
GSS
R
G
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
Min. Typ. Max. Units
100
–––
–––
2.0
–––
–––
–––
–––
–––
–––
0.11
11.3
–––
–––
–––
–––
–––
0.6
–––
–––
13.9
4.0
20
250
100
-100
–––
Conditions
V V
GS
= 0V, I
D
= 250μA
V/°C Reference to 25°C, I
D
= 5mA
mΩ V
GS
= 10V, I
D
= 37A
V V
DS
= V
GS
, I
D
= 100μA
μA
V
DS
= 100V, V
GS
= 0V
V
DS
= 80V, V
GS
= 0V, T
J
= 125°C
nA V
GS
= 20V
V
GS
= -20V
Ω
f
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Q
g
Q
gs
Q
gd
Q
sync
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
eff. (ER)
C
oss
eff. (TR)
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Q
g
- Q
gd
)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
Min. Typ. Max. Units
100
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
58
14
18
40
13
32
28
28
3180
220
120
260
325
–––
87
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
Conditions
V
DS
= 25V, I
D
= 37A
I
D
= 37A
V
DS
=50V
V
GS
= 10V
I
D
= 37A, V
DS
=0V, V
GS
= 10V
V
DD
= 65V
I
D
= 37A
R
G
=2.7Ω
V
GS
= 10V
V
GS
= 0V
V
DS
= 50V
ƒ = 1.0MHz, See Fig.5
V
GS
= 0V, V
DS
= 0V to 80V , See Fig.11
V
GS
= 0V, V
DS
= 0V to 80V
f
ns
f
pF
f
g
hÃ
h
gÃ
Diode Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Forward Turn-On Time
Min. Typ. Max. Units
–––
–––
–––
–––
61
250
A
A
Conditions
MOSFET symbol
showing the
integral reverse
G
S
D
Ã
––– –––
1.3
V
–––
54
81
ns
–––
60
90
–––
95
140
nC
T
J
= 125°C
––– 130 195
–––
3.3
–––
A T
J
= 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode.
T
J
= 25°C, I
S
= 37A, V
GS
= 0V
T
J
= 25°C
V
R
= 85V,
T
J
= 125°C
I
F
= 37A
di/dt = 100A/μs
T
J
= 25°C
f
f
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.192mH
R
G
= 25Ω, I
AS
= 37A, V
GS
=10V. Part not recommended for use
above this value.
I
SD
≤
37A, di/dt
≤
1550A/μs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
Pulse width
≤
400μs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
R
θ
is measured at T
J
approximately 90°C.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
2
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IRFS/SL4510PbF
1000
TOP
1000
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
VGS
15V
10V
6.0V
5.0V
4.8V
4.5V
4.3V
4.0V
TOP
100
BOTTOM
VGS
15V
10V
6.0V
5.0V
4.8V
4.5V
4.3V
4.0V
10
10
4.0V
1
4.0V
0.1
0.1
1
≤
60μs PULSE WIDTH
Tj = 25°C
10
100
1
0.1
1
≤
60μs PULSE WIDTH
Tj = 175°C
10
100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
1000
Fig 2.
Typical Output Characteristics
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current
(Α)
2.5
ID = 37A
VGS = 10V
100
TJ = 175°C
10
2.0
1.5
TJ = 25°C
1
1.0
VDS = 50V
≤
60μs PULSE WIDTH
0.1
2.0
3.0
4.0
5.0
6.0
7.0
0.5
0.0
-60 -40 -20 0
20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (°C)
Fig 3.
Typical Transfer Characteristics
100000
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Fig 4.
Normalized On-Resistance vs. Temperature
14
VGS, Gate-to-Source Voltage (V)
ID= 37A
VDS = 80V
VDS = 50V
VDS = 20V
12
10
8
6
4
2
0
C, Capacitance (pF)
10000
Ciss
1000
Coss
Crss
100
10
1
10
100
0
20
40
60
80
VDS, Drain-to-Source Voltage (V)
QG Total Gate Charge (nC)
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFS/SL4510PbF
1000
1000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS (on)
ISD, Reverse Drain Current (A)
100
100
1msec
10
TJ = 175°C
10
100μsec
TJ = 25°C
1
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
1
10
VDS, Drain-toSource Voltage (V)
DC
VGS = 0V
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
100
VSD, Source-to-Drain Voltage (V)
70
60
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 8.
Maximum Safe Operating Area
125
Id = 5mA
120
115
110
105
100
95
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Temperature ( °C )
ID, Drain Current (A)
50
40
30
20
10
0
25
50
75
100
125
150
175
TJ , Junction Temperature (°C)
Fig 9.
Maximum Drain Current vs.
Case Temperature
1.2
Fig 10.
Drain-to-Source Breakdown Voltage
600
EAS , Single Pulse Avalanche Energy (mJ)
1.0
500
400
300
200
100
0
25
50
75
100
0.8
ID
TOP
4.7A
12A
BOTTOM 37A
Energy (μJ)
0.6
0.4
0.2
0.0
0
20
40
60
80
100
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting TJ , Junction Temperature (°C)
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy vs. DrainCurrent
4
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IRFS/SL4510PbF
10
Thermal Response ( ZthJC ) °C/W
1
D = 0.50
0.20
0.1
0.10
0.05
0.02
0.01
SINGLE PULSE
( THERMAL RESPONSE )
1E-005
0.0001
0.001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.01
0.1
0.01
0.001
1E-006
t1 , Rectangular Pulse Duration (sec)
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Duty Cycle = Single Pulse
0.01
Avalanche Current (A)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
ΔTj
= 150°C and
Tstart =25°C (Single Pulse)
10
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
ΔΤ
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
tav (sec)
1.0E-03
1.0E-02
1.0E-01
Fig 14.
Typical Avalanche Current vs.Pulsewidth
140
120
100
80
60
40
20
0
25
50
75
100
125
150
175
EAR , Avalanche Energy (mJ)
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 37A
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
ΔT
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/
Z
thJC
I
av
= 2DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Starting TJ , Junction Temperature (°C)
Fig 15.
Maximum Avalanche Energy vs. Temperature
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