Si5338
I
2
C - P
R O GRA MM A B LE
A
NY
- F
R E Q U E N C Y
, A
NY
- O
UTPUT
Q
UAD
C
LOCK
G
ENERATOR
Features
Low power MultiSynth™ technology
enables independent, any-frequency
synthesis on four differential output
drivers
PCIe Gen 1/2/3/4 Common Clock and
Gen 3 SRNS compliant
Highly-configurable output drivers with
up to four differential outputs, eight
single-ended clock outputs, or a
combination of both
Low phase jitter of 0.7 ps RMS typ
High precision synthesis allows true
zero ppm frequency accuracy on all
outputs
Flexible input reference:
External
Single supply core with excellent
PSRR: 1.8, 2.5, 3.3 V
Independent frequency increment/
decrement feature enables
glitchless frequency adjustments in
1 ppm steps
Independent phase adjustment on
each of the output drivers with an
accuracy of <20 ps steps
Highly configurable spread
spectrum (SSC) on any output:
frequency from 5 to 350 MHz
Any spread from 0.5 to 5.0%
Any modulation rate from 33 to
63 kHz
Any
Ordering Information:
See page 42.
Pin Assignments
RSVD_GND
CLK0A
CLK0B
VDD
VDDO0
20
Independently configurable outputs
support any frequency or format:
LVPECL/LVDS:
HCSL:
0.16 to 710 MHz
0.16 to 250 MHz
CMOS: 0.16 to 200 MHz
SSTL/HSTL: 0.16 to 350 MHz
Independent output voltage per driver:
1.5, 1.8, 2.5, or 3.3 V
I
2
C/SMBus compatible interface
Easy to use programming software
Small size: 4 x 4 mm, 24-QFN
Low power: 45 mA core supply typ
Wide temperature range: –40 to
+85 °C
24
23
22
21
19
18
CLK1A
17
CLK1B
16
VDDO1
15
VDDO2
14
CLK2A
13
CLK2B
IN1
1
IN2
2
IN3
3
IN4
4
IN5
5
GND
GND
Pad
Applications
IN6
6
Ethernet switch/router
PCIe Gen1/2/3/4
Broadcast video/audio timing
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fibre Channel, SAN
Telecom line cards
1 GbE and 10 GbE
7
8
9
10
11
12
INTR
Description
The Si5338 is a high-performance, low-jitter clock generator capable of
synthesizing any frequency on each of the device's four output drivers. This timing
IC is capable of replacing up to four different frequency crystal oscillators or
operating as a frequency translator. Using its patented MultiSynth™ technology,
the Si5338 allows generation of four independent clocks with 0 ppm precision.
Each output clock is independently configurable to support various signal formats
and supply voltages. The Si5338 provides low-jitter frequency synthesis in a
space-saving 4 x 4 mm QFN package. The device is programmable via an I
2
C/
SMBus-compatible serial interface and supports operation from a 1.8, 2.5, or
3.3 V core supply. I
2
C device programming is made easy with the ClockBuilder™
Desktop software available at
www.silabs.com/ClockBuilder.
Measuring PCIe
clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool.
Download it for free at
www.silabs.com/pcie-learningcenter.
Rev. 1.6 12/15
Copyright © 2015 by Silicon Laboratories
VDDO3
VDD
CLK3B
CLK3A
SCL
SDA
crystal: 8 to 30 MHz
CMOS input: 5 to 200 MHz
SSTL/HSTL input: 5 to 350 MHz
Differential input: 5 to 710 MHz
External feedback mode allows
zero-delay mode
Loss of lock and loss of signal
alarms
Top View
Si5338
Si5338
Functional Block Diagram
VDD
Synthesis
Stage 1
(PLL)
ref
Osc
noclk
P1DIV_IN
Synthesis
Stage 2
MultiSynth
÷M0
Output
Stage
VDDO0
÷
R0
CLK0A
CLK0B
VDDO1
IN1
IN2
IN3
÷P1
P2DIV_IN
Phase
Frequency
Detector
fb
Loop
Filter
VCO
MultiSynth
÷M1
÷
R1
CLK1A
CLK1B
VDDO2
IN4
IN5
IN6
÷P2
noclk
MultiSynth
÷M2
MultiSynth
÷N
MultiSynth
÷M3
÷
R2
CLK2A
CLK2B
VDDO3
Control & Memory
OEB/PINC/FINC
I2C_LSB/PDEC/FDEC
SCL
SDA
INTR
NVM
Control
(OTP)
÷
R3
CLK3A
CLK3B
RAM
2
Rev. 1.6
Si5338
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2. Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3. Synthesis Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5. Configuring the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6. Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9. Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10. Features of the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4. Applications of the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1. Free-Running Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2. Synchronous Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3. Configurable Buffer and Level Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2
5. I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6. Si5338 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8. Device Pinout by Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10. Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11.1. Si5338 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Rev. 1.6
3
Si5338
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(V
DD
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Ambient Temperature
Symbol
T
A
Test Condition
Min
–40
2.97
Typ
25
3.3
2.5
1.8
—
Max
85
3.63
2.75
1.98
3.63
Unit
°C
V
V
V
V
Core Supply Voltage
V
DD
2.25
1.71
Output Buffer Supply
Voltage
V
DDOn
1.4
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. Absolute Maximum Ratings
1
Parameter
DC Supply Voltage
Storage Temperature Range
ESD Tolerance
ESD Tolerance
ESD Tolerance
Latch-up Tolerance
Junction Temperature
Peak Soldering Reflow Temperature
2
T
J
Symbol
V
DD
T
STG
HBM
(100 pF, 1.5 k)
CDM
MM
Test Condition
Value
–0.5 to 3.8
–55 to 150
2.5
550
175
Unit
V
°C
kV
V
V
JESD78 Compliant
150
260
°C
°C
Notes:
1.
Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2.
Refer to JEDEC J-STD-020 standard for more information.
4
Rev. 1.6
Si5338
Table 3. DC Characteristics
(V
DD
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Core Supply Current
Core Supply Current
(Buffer Mode)
Symbol
I
DD
I
DDB
Test Condition
100 MHz on all outputs,
25 MHz refclk
50 MHz refclk
LVPECL, 710 MHz
LVDS, 710 MHz
HCSL, 250 MHz
2 pF load
CML, 350 MHz
SSTL, 350 MHz
Min
—
—
—
—
—
—
—
—
—
—
—
—
Typ
45
12
—
—
—
12
—
6
13
10
7
—
Max
60
—
30
8
20
—
19
9
18
14
10
19
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Output Buffer Supply Current
I
DDOx
CMOS, 50 MHz
15 pF load
1
CMOS, 200 MHz
1,2
3.3 V VDD0
CMOS, 200 MHz
1,2
2.5 V
CMOS, 200 MHz
1,2
1.8 V
HSTL, 350 MHz
Notes:
1.
Single CMOS driver active.
2.
Measured into a 5” 50
trace with 2 pF load.
Table 4. Thermal Characteristics
Parameter
Thermal Resistance
Junction to Ambient
Thermal Resistance
Junction to Case
Symbol
JA
JC
Test Condition
Still Air
Still Air
Value
37
10
Unit
°C/W
°C/W
Rev. 1.6
5
FPGA/CPLD
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