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LCMXO3LF-9400E-5BG256C: 产品描述FPGA MACHXO3 Family 9400 Cells 65nm Technology 1.2V Automotive 256-Pin CABGA; 文件大小3MB，共96页; 制造商Lattice(莱迪斯); 官网地址http://www.latticesemi.com; 标准

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LCMXO3LF-9400E-5BG256C概述

FPGA MACHXO3 Family 9400 Cells 65nm Technology 1.2V Automotive 256-Pin CABGA

LCMXO3LF-9400E-5BG256C规格参数

参数名称	属性值
ECCN (US)	3A991.d
Family Name	MACHXO3
Process Technology	65nm
Number of I/O Banks	6
Operating Supply Voltage (V)	1.2
Logic Elements	9400
Program Memory Type	Flash
Embedded Memory (Kbit)	432
Total Number of Block RAM	73
Device Logic Units	9400
Device Number of DLLs/PLLs	2
Programmability	Yes
Reprogrammability Support	Yes
Copy Protection	No
In-System Programmability	Yes
Minimum Operating Supply Voltage (V)	1.14
Maximum Operating Supply Voltage (V)	1.26
I/O Voltage (V)	3.3\|2.5\|1.8\|1.5\|1.2
Supplier Package	CABGA
Pin Count	256
Mounting	Surface Mount
Package Height	0.65(Min)
Package Length	14
Package Width	14
PCB changed	256

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MachXO3 Family

Data Sheet

FPGA-DS-02032-3.0

June 2021

MachXO3 Family

Data Sheet

Contents

Acronyms in This Document ................................................................................................................................................. 7

1. Introduction .................................................................................................................................................................. 9

1.1.

Features ............................................................................................................................................................ 10

1.1.1. Solutions ....................................................................................................................................................... 10

1.1.2. Flexible Architecture .................................................................................................................................... 10

1.1.3. Advanced Packaging ..................................................................................................................................... 10

1.1.4. Pre-Engineered Source Synchronous I/O ..................................................................................................... 10

1.1.5. High Performance, Flexible I/O Buffer ......................................................................................................... 10

1.1.6. Flexible On-Chip Clocking ............................................................................................................................. 10

1.1.7. Non-volatile, Multi-time Programmable ...................................................................................................... 10

1.1.8. TransFR Reconfiguration .............................................................................................................................. 10

1.1.9. Enhanced System Level Support .................................................................................................................. 10

1.1.10. Applications .................................................................................................................................................. 10

1.1.11. Low Cost Migration Path .............................................................................................................................. 10

2. Architecture ................................................................................................................................................................ 12

2.1.

Architecture Overview ...................................................................................................................................... 12

2.2.

PFU Blocks ......................................................................................................................................................... 14

2.2.1. Slices ............................................................................................................................................................. 14

2.2.2. Modes of Operation ..................................................................................................................................... 16

2.2.3. RAM Mode ................................................................................................................................................... 16

2.2.4. ROM Mode ................................................................................................................................................... 16

2.3.

Routing .............................................................................................................................................................. 17

2.4.

Clock/Control Distribution Network .................................................................................................................. 17

2.4.1. sysCLOCK Phase Locked Loops (PLLs) ........................................................................................................... 19

2.5.

sysMEM Embedded Block RAM Memory.......................................................................................................... 22

2.5.1. sysMEM Memory Block ................................................................................................................................ 22

2.5.2. Bus Size Matching......................................................................................................................................... 22

2.5.3. RAM Initialization and ROM Operation ........................................................................................................ 22

2.5.4. Memory Cascading ....................................................................................................................................... 22

2.5.5. Single, Dual, Pseudo-Dual Port and FIFO Modes .......................................................................................... 23

2.5.6. FIFO Configuration ....................................................................................................................................... 24

2.5.7. Memory Core Reset...................................................................................................................................... 24

2.5.8. EBR Asynchronous Reset .............................................................................................................................. 25

2.6.

Programmable I/O Cells (PIC) ............................................................................................................................ 26

2.7.

PIO ..................................................................................................................................................................... 28

2.7.1. Input Register Block ..................................................................................................................................... 28

2.7.2. Output Register Block................................................................................................................................... 28

2.7.3. Tri-state Register Block................................................................................................................................. 29

2.8.

Input Gearbox ................................................................................................................................................... 29

2.9.

Output Gearbox ................................................................................................................................................ 31

2.10. sysI/O Buffer...................................................................................................................................................... 33

2.10.1. Typical I/O Behavior during Power-up ......................................................................................................... 33

2.10.2. Supported Standards .................................................................................................................................... 33

2.10.3. sysI/O Buffer Banks ...................................................................................................................................... 35

2.11. Hot Socketing .................................................................................................................................................... 36

2.12. On-chip Oscillator.............................................................................................................................................. 36

2.13. Embedded Hardened IP Functions .................................................................................................................... 36

2.13.1. Hardened I

C IP Core .................................................................................................................................... 37

2.13.2. Hardened SPI IP Core.................................................................................................................................... 38

2.13.3. Hardened Timer/Counter ............................................................................................................................. 40

2.14. User Flash Memory (UFM) ................................................................................................................................ 41

2.15. Standby Mode and Power Saving Options ........................................................................................................ 41

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FPGA-DS-02032-3.0

MachXO3 Family

Data Sheet

2.16. Power On Reset .................................................................................................................................................42

2.17. Configuration and Testing .................................................................................................................................42

2.17.1. IEEE 1149.1-Compliant Boundary Scan Testability .......................................................................................42

2.17.2. Device Configuration ....................................................................................................................................42

2.18. TraceID ..............................................................................................................................................................44

2.19. Density Shifting .................................................................................................................................................44

2.20. MachXO3LF to MachXO3L Low Cost Migration Path ........................................................................................44

3. DC and Switching Characteristics................................................................................................................................45

3.1.

Absolute Maximum Rating ................................................................................................................................45

3.2.

Recommended Operating Conditions ...............................................................................................................45

3.3.

Power Supply Ramp Rates.................................................................................................................................45

3.4.

Power-On-Reset Voltage Levels ........................................................................................................................46

3.5.

Hot Socketing Specifications .............................................................................................................................46

3.6.

Programming/Erase Specifications ...................................................................................................................46

3.7.

ESD Performance...............................................................................................................................................47

3.8.

DC Electrical Characteristics ..............................................................................................................................48

3.9.

Static Supply Current – C/E Devices ..................................................................................................................49

3.10. Programming and Erase Supply Current – C/E Devices .....................................................................................49

3.11. sysI/O Recommended Operating Conditions .....................................................................................................50

3.12. sysI/O Single-Ended DC Electrical Characteristics ..............................................................................................50

3.13. sysI/O Differential Electrical Characteristics .....................................................................................................51

3.13.1. LVDS..............................................................................................................................................................51

3.13.2. LVDS Emulation ............................................................................................................................................52

3.13.3. BLVDS ...........................................................................................................................................................53

3.13.4. LVPECL ..........................................................................................................................................................54

3.13.5. MIPI D-PHY Emulation ..................................................................................................................................55

3.14. Typical Building Block Function Performance – C/E Devices.............................................................................57

3.14.1. Pin-to-Pin Performance (LVCMOS25 12 mA Drive) ......................................................................................57

3.14.2. Register-to-Register Performance ................................................................................................................57

3.15. Derating Logic Timing ........................................................................................................................................58

3.16. Maximum sysI/O Buffer Performance...............................................................................................................58

3.17. MachXO3L/LF External Switching Characteristics – C/E Devices ......................................................................58

3.18. sysCLOCK PLL Timing .........................................................................................................................................68

3.19. Oscillator Output Frequency .............................................................................................................................69

3.20. NVCM/Flash Download Time ............................................................................................................................70

3.21. JTAG Port Timing Specifications ........................................................................................................................70

3.22. sysCONFIG Port Timing Specifications...............................................................................................................71

3.23. I

C Port Timing Specifications ............................................................................................................................72

3.24. SPI Port Timing Specifications ...........................................................................................................................72

3.25. Switching Test Conditions .................................................................................................................................72

4. Signal Descriptions ......................................................................................................................................................74

4.1.

Pin Information Summary .................................................................................................................................75

5. MachXO3 Part Number Description ...........................................................................................................................80

6. Ordering Information..................................................................................................................................................81

6.1.

MachXO3L Ultra Low Power Commercial and Industrial Grade Devices, Halogen Free (RoHS) Packaging ......81

6.2.

MachXO3LF Ultra Low Power Commercial and Industrial Grade Devices, Halogen Free (RoHS) Packaging ....84

6.3.

MachXO3LF Ultra Low Power Automotive Grade Devices, Halogen Free (RoHS) Packaging ............................87

References ..........................................................................................................................................................................88

Revision History ..................................................................................................................................................................89

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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02032-3.0

MachXO3 Family

Data Sheet

Figures

Figure 2.1. Top View of the MachXO3L/LF-1300 Device .................................................................................................... 12

Figure 2.2. Top View of the MachXO3L/LF-4300 Device .................................................................................................... 13

Figure 2.3. PFU Block Diagram ............................................................................................................................................ 14

Figure 2.4. Slice Diagram .................................................................................................................................................... 15

Figure 2.5. Primary Clocks for MachXO3L/F Devices .......................................................................................................... 18

Figure 2.6. Secondary High Fanout Nets for MachXO3L/F Devices .................................................................................... 19

Figure 2.7. PLL Diagram ...................................................................................................................................................... 20

Figure 2.8. sysMEM Memory Primitives ............................................................................................................................. 23

Figure 2.9. Memory Core Reset .......................................................................................................................................... 25

Figure 2.10. EBR Asynchronous Reset (Including GSR) Timing Diagram............................................................................. 25

Figure 2.11. Group of Four Programmable I/O Cells .......................................................................................................... 27

Figure 2.12. Output Register Block Diagram (PIO on the Left, Top and Bottom Edges) ..................................................... 29

Figure 2.13. Input Gearbox ................................................................................................................................................. 30

Figure 2.14. Output Gearbox .............................................................................................................................................. 32

Figure 2.15. MachXO3L/LF-1300 in 256 Ball Packages, MachXO3L/LF-2100, MachXO3L/LF-4300, MachXO3L/LF-6900 and

MachXO3L/LF-9400 Banks I/O Banks .............................................................................................................. 35

Figure 2.16. MachXO3L/LF-640 and MachXO3L/LF-1300 Banks ........................................................................................ 35

Figure 2.17. Embedded Function Block Interface ............................................................................................................... 37

Figure 2.18. I

C Core Block Diagram ................................................................................................................................... 37

Figure 2.19. SPI Core Block Diagram ................................................................................................................................... 39

Figure 2.20. Timer/Counter Block Diagram ........................................................................................................................ 40

Figure 3.1. LVDS Using External Resistors (LVDS25E) ......................................................................................................... 52

Figure 3.2. BLVDS Multi-point-Output Example ................................................................................................................. 53

Figure 3.3. Differential LVPECL ........................................................................................................................................... 54

Figure 3.4. MIPI D-PHY Input Using External Resistors ....................................................................................................... 55

Figure 3.5. MIPI D-PHY Output Using External Resistors .................................................................................................... 56

Figure 3.6.Receiver GDDR71_RX. Waveforms .................................................................................................................... 68

Figure 3.7. Transmitter GDDR71_TX. Waveforms .............................................................................................................. 68

Figure 3.8. JTAG Port Timing Waveforms ........................................................................................................................... 71

Figure 3.9. Output Test Load, LVTTL and LVCMOS Standards ............................................................................................ 73

Tables

Table 1.1. MachXO3L/LF Family Selection Guide ............................................................................................................... 11

Table 2.1. Resources and Modes Available per Slice .......................................................................................................... 14

Table 2.2. Slice Signal Descriptions ..................................................................................................................................... 15

Table 2.3. Number of Slices Required For Implementing Distributed RAM ....................................................................... 16

Table 2.4. PLL Signal Descriptions ....................................................................................................................................... 21

Table 2.5. sysMEM Block Configurations ............................................................................................................................ 22

Table 2.6. EBR Signal Descriptions ...................................................................................................................................... 23

Table 2.7. Programmable FIFO Flag Ranges ....................................................................................................................... 24

Table 2.8. PIO Signal List ..................................................................................................................................................... 28

Table 2.9. Input Gearbox Signal List ................................................................................................................................... 29

Table 2.10. Output Gearbox Signal List .............................................................................................................................. 31

Table 2.11. Supported Input Standards .............................................................................................................................. 34

Table 2.12. Supported Output Standards ........................................................................................................................... 34

Table 2.13. Available MCLK Frequencies ............................................................................................................................ 36

Table 2.14. I

C Core Signal Description ............................................................................................................................... 38

Table 2.15. SPI Core Signal Description .............................................................................................................................. 39

Table 2.16. Timer/Counter Signal Description.................................................................................................................... 40

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02032-3.0

LCMXO3LF-9400E-5BG256C相似产品对比

	LCMXO3LF-9400E-5BG256C	LCMXO3LF-9400E-6BG484I	LCMXO3LF-9400E-5BG400I	LCMXO3LF-9400E-5BG256I
描述	FPGA MACHXO3 Family 9400 Cells 65nm Technology 1.2V Automotive 256-Pin CABGA	FPGA MACHXO3 Family 9400 Cells 65nm Technology 1.2V Automotive 484-Pin caBGA	FPGA MACHXO3 Family 9400 Cells 65nm Technology 1.2V Automotive 400-Pin CABGA	FPGA MACHXO3 Family 9400 Cells 65nm Technology 1.2V Automotive 256-Pin CABGA
ECCN (US)	3A991.d	3A991.d	3A991.d	3A991.d
Family Name	MACHXO3	MACHXO3	MACHXO3	MACHXO3
Process Technology	65nm	65nm	65nm	65nm
Number of I/O Banks	6	6	6	6
Operating Supply Voltage (V)	1.2	1.2	1.2	1.2
Logic Elements	9400	9400	9400	9400
Program Memory Type	Flash	Flash	Flash	Flash
Embedded Memory (Kbit)	432	432	432	432
Total Number of Block RAM	73	73	73	73
Device Logic Units	9400	9400	9400	9400
Device Number of DLLs/PLLs	2	2	2	2
Programmability	Yes	Yes	Yes	Yes
Reprogrammability Support	Yes	Yes	Yes	Yes
Copy Protection	No	No	No	No
In-System Programmability	Yes	Yes	Yes	Yes
Minimum Operating Supply Voltage (V)	1.14	1.14	1.14	1.14
Maximum Operating Supply Voltage (V)	1.26	1.26	1.26	1.26
I/O Voltage (V)	3.3\|2.5\|1.8\|1.5\|1.2	1.2\|1.5\|1.8\|2.5\|3.3	3.3\|2.5\|1.2\|1.5\|1.8	1.2\|1.5\|1.8\|2.5\|3.3
Supplier Package	CABGA	caBGA	CABGA	CABGA
Pin Count	256	484	400	256
Mounting	Surface Mount	Surface Mount	Surface Mount	Surface Mount
Package Height	0.65(Min)	0.65(Min)	1	0.65(Min)
Package Length	14	19	17	14
Package Width	14	19	17	14
PCB changed	256	484	400	256
Part Status	-	Active	Active	Active

LCMXO3LF-9400E-5BG256C

LCMXO3LF-9400E-5BG256C在线购买

LCMXO3LF-9400E-5BG256C概述

LCMXO3LF-9400E-5BG256C规格参数

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LCMXO3LF-9400E-5BG256C相似产品对比

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