S i 5 3 5 / 5 36
R
EVISION
D
U
L T R A
L
O W
J
ITTER
C
RYSTAL
O
SCILLATOR
(XO)
Features
Available with select frequencies from
Available with LVPECL and
100 MHz to 312.5 MHz
LVDS outputs
3
rd
generation DSPLL
®
with superior
3.3 and 2.5 V supply options
Industry-standard 5 x 7 mm
jitter performance and high-power
package and pinout
supply noise rejection
Pb-free/RoHS-compliant
3x better frequency stability than
SAW-based oscillators
Si5602
Applications
Ordering Information:
See page 7.
10/40/100G data centers
10G Ethernet switches/routers
Fibre channel/SAS/storage
Enterprise servers
Networking
Telecommunications
Description
The Si535/536 XO utilizes Silicon Labs’ advanced DSPLL
®
circuitry to
provide an ultra low jitter clock at high-speed differential frequencies. Unlike a
traditional XO, where a different crystal is required for each output frequency,
the Si535/536 uses one fixed crystal to provide a wide range of output
frequencies. This IC based approach allows the crystal resonator to provide
exceptional frequency stability and reliability. In addition, DSPLL clock
synthesis provides superior supply noise rejection, simplifying the task of
generating low jitter clocks in noisy environments typically found in
communication systems. The Si535/536 IC based XO is factory programmed
at time of shipment, thereby eliminating long lead times associated with
custom oscillators.
Pin Assignments:
See page 6.
(Top View)
NC
1
6
V
DD
OE
2
5
CLK–
GND
3
4
CLK+
Si535
Functional Block Diagram
V
DD
CLK– CLK+
OE
1
6
V
DD
NC
2
5
CLK–
GND
3
4
CLK+
Si536
Fixed
Frequency
XO
100–312.5 MHz
DSPLL
®
Clock Synthesis
OE
GND
Rev. 1.2 5/16
Copyright © 2016 by Silicon Laboratories
Si535/536
Si535/536
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
1
Symbol
V
DD
Test Condition
3.3 V option
2.5 V option
Supply Current
I
DD
Output enabled
LVPECL
LVDS
Tristate mode
Output Enable (OE)
2
Min
2.97
2.25
—
—
—
0.75 x V
DD
—
–40
Typ
3.3
2.5
111
90
60
—
—
—
Max
3.63
2.75
121
98
75
—
0.5
85
Unit
V
V
mA
mA
V
V
°C
V
IH
V
IL
Operating Temperature Range
T
A
Notes:
1.
Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.
2.
OE pin includes a 17 k pullup resistor to V
DD
.
Table 2. CLK± Output Frequency Characteristics
Parameter
Nominal Frequency
1
Initial Accuracy
Temperature Stability
1,2
Aging
f
a
Total Stability
2
Frequency drift over first year
Frequency drift over 20 year
life
Temp stability = ±20 ppm
Temp stability = ±7 ppm
Powerup Time
3
t
OSC
T
A
= –40°C — +85°C
Symbol
f
O
f
i
Test Condition
LVPECL/LVDS
Measured at +25 °C at time of
shipping
Min
100
—
–7
–20
—
—
—
—
—
Typ
—
±1.5
—
—
—
—
—
—
—
Max
312.5
—
+7
+20
±3
±10
±31.5
Unit
MHz
ppm
ppm
ppm
ppm
ppm
20
10
ms
Notes:
1.
See Section 3. "Ordering Information" on page 7 for the list of available frequencies.
2.
Selectable parameter specified by part number.
3.
Time from powerup or tristate mode to f
O
.
2
Rev. 1.2
Si535/536
Table 3. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option
1
Symbol
V
O
V
OD
V
SE
Test Condition
Mid-level
Swing (diff)
Swing (Single-ended)
Mid-level
Swing (diff)
Min
V
DD
– 1.42
1.1
0.55
1.125
0.5
Typ
—
Max
V
DD
– 1.25
1.9
0.95
1.275
0.9
Unit
V
V
PP
V
PP
V
V
PP
—
—
1.20
0.7
LVDS Output Option
2
V
O
V
OD
Rise/Fall time (20/80%)
Symmetry (duty cycle)
t
R,
t
F
—
Differential
45
—
—
350
55
ps
%
SYM
Notes:
1.
50
to V
DD
– 2.0 V.
2.
R
term
= 100
(differential).
Rev. 1.2
3
Si535/536
Table 4. CLK± Output Phase Jitter
Parameter
LVPECL/LVDS Phase Jitter*
(RMS)
Symbol
Test Condition
10 kHz to 1 MHz (data center)
12 kHz to 20 MHz brickwall
Min
—
—
Typ
0.19
0.25
Max
0.35
0.40
Unit
ps
ps
J
*Note:
Applies to output frequencies: 156.25 MHz.
Table 5. CLK± Output Period Jitter
Parameter
LVPECL/LVDS Period Jitter*
Symbol
J
PER
Test Condition
RMS
Peak-to-Peak
Min
—
—
Typ
2
14
Max
—
—
Unit
ps
ps
*Note:
N = 1000 cycles.
Figure 1. Si535/536 Typical Phase Noise at 156.25 MHz
4
Rev. 1.2
Si535/536
Table 6. Environmental Compliance
The Si535/536 meets the following qualification test requirements.
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross & Fine Leak
Resistance to Solder Heat
Moisture Sensitivity Level
Contact Pads
Conditions/Test Method
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2036
J-STD-020, MSL1
Gold over Nickel
Table 7. Thermal Characteristics
(Typical values TA = 25 ºC, V
DD
= 3.3 V)
Parameter
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
Ambient Temperature
Junction Temperature
Symbol
JA
JC
T
A
T
J
Test Condition
Still Air
Still Air
Min
—
—
–40
—
Typ
84.6
38.8
—
—
Max
—
—
85
125
Unit
°C/W
°C/W
°C
°C
Table 8. Absolute Maximum Ratings
1
Parameter
Maximum Operating Temperature
Supply Voltage, 2.5/3.3 V Option
Input Voltage (any input pin)
Storage Temperature
ESD Sensitivity (HBM, per JESD22-A114)
Soldering Temperature (Pb-free profile)
2
Soldering Temperature Time @ T
PEAK
(Pb-free profile)
2
Symbol
T
AMAX
V
DD
V
I
T
S
ESD
T
PEAK
t
P
Rating
85
–0.5 to +3.8
–0.5 to V
DD
+ 0.3
–55 to +125
2500
260
20–40
Unit
°C
V
V
°C
V
°C
seconds
Notes:
1.
Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2.
The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO
for further information, including soldering profiles.
Rev. 1.2
5
FPGA/CPLD
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