电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

PLL650-09SC

产品描述Low Cost Network LAN Clock
文件大小225KB,共5页
制造商PLL (PhaseLink Corporation)
下载文档 选型对比 全文预览

PLL650-09SC概述

Low Cost Network LAN Clock

文档预览

下载PDF文档
PLL650-09
Low Cost Network LAN Clock
FEATURES
PIN CONFIGURATION
XIN
XOUT
G ND
VDD
50MHz
G ND
50MHz
1
2
16
15
VDD
VDD
N/C
G ND
G ND
GND
VDD
50MHz
Full CMOS output swing with 40-mA output drive
capability. 25-mA output drive at TTL level.
Advanced, low power, sub-micron CMOS processes.
25MHz fundamental crystal or clock input.
4 outputs fixed at 50MHz .
Zero PPM synthesis error in all clocks.
Ideal for Network switches.
3.3V operation.
Available in 16-Pin 150mil SOIC
.
P LL 650-09
3
4
5
6
7
8
14
13
12
11
10
9
DESCRIPTIONS
The PLL 650-09 is a low cost, low jitter, and high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, the chip
accepts 25.0 MHz crystal, and produces multiple output
clocks for networking chips.
50MHz
BLOCK DIAGRAM
4
XIN
XOUT
XTAL
OS C
50MHz
C ontrol
Logic
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 09/19/02 Page 1

PLL650-09SC相似产品对比

PLL650-09SC PLL650-09 PLL650-09SI PLL650-09SM
描述 Low Cost Network LAN Clock Low Cost Network LAN Clock Low Cost Network LAN Clock Low Cost Network LAN Clock

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 110  1445  2480  796  2020  3  30  50  17  41 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved