PLL620-30
PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)
FEATURES
•
•
•
•
•
•
•
•
65MHz to 130MHz Crystal input.
Output range: 32.5MHz – 130MHz (no PLL).
Low Injection Power for crystal, 50uW.
Complementary outputs: PECL or LVDS.
Selectable OE Logic
Supports 2.5V or 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
62 mil
DIE CONFIGURATION
65 mil
Reserved
Reserved
OESEL^
VDD
VDD
VDD
VDD
N/C
(1550,1475)
17
16
25
24
23
22
21
20
19
18
GNDBUF
N/C
LVDSB
PECLB
VDDBUF
VDDBUF
PECL
LVDS
OUTSEL^
XIN
XOUT
N/C
S2^
OE
CTRL
N/C
26
27
Die ID:
A2020-20A
15
28
14
DESCRIPTION
The PLL620-30 is a XO IC specifically designed to
drive fundamental or 3
rd
OT crystals from 65MHz to
130MHz, with selectable PECL or LVDS outputs and
OE logic (enable high or enable low). Its design was
optimized to tolerate higher limits of interelectrode
capacitance and bonding capacitance to improve
yield. It achieves very low current into the crystal
resulting in better overall stability.
13
29
12
11
30
C502A
31
1
2
3
4
5
6
7
8
10
9
Reserved
Y
(0,0)
X
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
OUTPUT SELECTION AND ENABLE
OUTSEL
(Pad #9)
0
1
Selected Output
LVDS
PECL (default)
OESEL
(Pad #25)
0
1 (default)
BLOCK DIAGRAM
OE
Q
XIN
XOUT
Oscillator
Amplifier
OE_CTRL
(Pad #30)
0
1
0
1
State
Tri-state
Output enabled (default)
Output enabled (default)
Tri-state
Pad #9, #25: Bond to GND to set to “0”. Internal pull up.
Pad #30: Logical states defined by PECL levels if OESEL is “1”
Logical states defined by CMOS levels if OESEL is “0”
Q
OUTPUT FREQUENCY SELECTOR
PLL620-30
S2
0
1(Default)*
*Internally set to ‘Default’ through 60K
Output
Input/2
Input
pull-up resistor
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/09/04 Page 1
GNDBUF
GNDBUF
GND
GND
GND
GND
GND
PLL620-30
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Built-in Capacitance
Inter-electrode capacitance
Oscillation Frequency
SYMBOL
CX+
CX-
C
0
OF
CONDITIONS
65MHz to 130MHz
(VDD=3.3V)
Fund.
MIN.
TYP.
MAX.
2
2
UNITS
pF
MHz
2.6
65
130
3. General Electrical Specifications
PARAMETERS
Supply Current (Loaded
Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
I
DD
V
DD
CONDITIONS
PECL/LVDS
@ 1.25V (LVDS)
@ V
DD
– 1.3V (PECL)
MIN.
TYP.
MAX.
100/80
UNITS
mA
V
%
mA
2.97
45
45
50
50
±50
3.63
55
55
4. Jitter Specifications
PARAMETERS
Period jitter RMS
Period jitter peak-to-peak
Integrated jitter RMS
CONDITIONS
77.76MHz
77.76MHz
Integrated 12 kHz to 20 MHz at 77.76MHz
MIN.
TYP.
2.5
18.5
0.5
MAX.
UNITS
ps
ps
ps
5. Phase Noise Specifications
PARAMETERS
Phase Noise relative
to carrier
FREQUENCY
77.76MHz
@10Hz
-75
@100Hz
-95
@1kHz
-125
@10kHz
-145
@100kHz
-155
UNITS
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/09/04 Page 2
PLL620-30
PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)
6. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V
DD
Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
SYMBOL
V
OD
∆V
OD
V
OH
V
OL
V
OS
∆V
OS
I
OXD
I
OSD
CONDITIONS
MIN.
247
-50
TYP.
355
1.4
1.1
1.2
3
±1
-5.7
MAX.
454
50
1.6
1.375
25
±10
-8
UNITS
mV
mV
V
V
V
mV
uA
mA
R
L
= 100
Ω
(see figure)
0.9
1.125
0
V
out
= V
DD
or GND
V
DD
= 0V
7. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
t
r
t
f
CONDITIONS
R
L
= 100
Ω
C
L
= 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Switching Test Circuit
OUT
C
L
= 10pF
50Ω
V
OD
V
OS
V
DIFF
R
L
= 100Ω
50Ω
C
L
= 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V
DIFF
20%
0V
80%
20%
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/09/04 Page 3
PLL620-30
PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)
8. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
V
OH
V
OL
CONDITIONS
R
L
= 50
Ω
to (V
DD
– 2V)
(see figure)
MIN.
V
DD
– 1.025
V
DD
– 1.900
MAX.
V
DD
– 0.750
V
DD
– 1.620
UNITS
V
V
9. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
t
r
t
f
CONDITIONS
@20/80% - PECL
@80/20% - PECL
MIN.
0.3
0.3
TYP.
0.6
0.5
MAX.
1.5
1.5
UNITS
ns
ns
PECL Levels Test Circuit
OUT
VDD
OUT
PECL Output Skew
50Ω
2.0V
50%
50Ω
OUT
OUT
t
SKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/09/04 Page 4
PLL620-30
PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)
PAD ASSIGNMENT
Pad #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
Optional GND
Optional GND
Optional GND
Optional GND
GND
Reserved
Optional GNDBUF
GNDBUF
OUTSEL
LVDS
PECL
VDDBUF
Optional VDDBUF
PECLB
LVDSB
Not connected
GNDBUF
Reserved
Reserved
Not connected
Optional VDD
Optional VDD
VDD
Optional VDD
OESEL
XIN
XOUT
Not connected
S2
OE_CTRL
Not connected
X (µm)
µ
248
361
473
587
702
874
1042
1171
1400
1400
1400
1400
1400
1400
1400
1400
1389
1232
1042
854
659
559
459
358
194
109
109
109
109
109
109
Y (µm)
µ
109
109
109
109
109
109
109
109
125
259
476
616
716
871
1089
1227
1365
1365
1365
1365
1365
1365
1365
1365
1365
1223
1017
858
646
397
181
Optional Ground.
Optional Ground.
Optional Ground.
Optional Ground.
Ground.
Reserved for future use.
Optional Ground, buffer circuitry.
Ground, buffer circuitry.
Output type selector. Internal pull up. See Output
Selection and Enable table on page 1. Internal pull
up.
LVDS output.
PECL output.
Power supply, buffer circuitry.
Optional Power supply, buffer circuitry.
Complementary PECL output.
Complementary LVDS output.
Not Connected.
Ground, buffer circuitry.
Reserved for future use.
Reserved for future use.
Not Connected.
Optional Power supply.
Optional Power supply.
Power supply.
Optional Power supply.
Used to choose between PECL and CMOS OE logic
levels. See Output Selection and Enable table on
page 1. Internal pull up
Crystal input. See Crystal Specifications on page 2.
Crystal output. See Crystal Specifications on page 2.
Not Connected.
Used to select output divider. Internal pull up.
Used to enable/disable the output(s). See Output
Selection and Enable table on page 1.
Not connected.
Description
Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/09/04 Page 5
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