AS4C128M32MD2-18BCN
AS4C128M32MD2-18BIN
Specifications
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Density : 4G bits
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Organization :
- 16M words x 32 bits x 8 banks
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Package :
- 134-ball FBGA
- Lead-free (RoHS compliant) and Halogen-free
Power supply :
- VDD1 = 1.8V (1.7V~1.95V)
- VDD2/VDDQ/VDDCA = 1.2V (1.14V~1.3V)
HSUL_12 interface (High Speed Unterminated Logic
1.2V)
Data rate :
- 1066Mbps RL=8
Burst lengths (BL) : 4, 8 and 16
Burst type (BT) : Sequential and interleave
Read Latency (RL) : 3, 4, 5, 6, 7, 8
Write Latency (WL) : 1, 2, 3, 4
Output driver impedance: 34.3/40/48/60/80/120
Ω
Operating case temperature range
- Commercial Tc = -25°C to +85°C
- Industrial Tc = -40°C to +85°C
Features
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JEDEC LPDDR2-S4B compliance
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Low power consumption
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Four-bit prefetch DDR architecture
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Eight internal banks for concurrent operation
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Double data rate architecture for command, address
and data Bus
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Bidirectional and differential data strobe per byte of
data (DQS and DQS)
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DQS is edge-aligned with data for READs, center-
aligned with data for WRITEs
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Differential clock inputs (CK and CK)
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Data mask (DM) for write data
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Programmable READ and WRITE latencies (RL/WL)
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Auto Refresh and Self Refresh
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Per-bank refresh for concurrent operation
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Partial-array self refresh (PASR)
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On-chip temperature sensor to control self refresh rate
for temperature compensated self refresh (TCSR)
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Deep power-down mode (DPD)
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Selectable output drive strength (DS)
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Clock stop capability
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DQ calibration offering specific DQ output patterns
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ZQ calibration
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Table 1. Ordering Information
Part Number
Org
Temperature
MaxClock (MHz)
533
533
Package
134-ball FBGA
134-ball FBGA
AS4C128M32MD2-18BCN
128Mx32
Commercial
-25°C to +85°C
AS4C128M32MD2-18BIN
128Mx32
Industrial
-40°C to +85°C
Table 2. Speed Grade Information
Speed Grade
Clock Frequency
DDR2L-1066
533MHz
RL
8
tRCD (ns)
18
tRP (ns)
18
Confidential
-2／103-
Rev.1.0 June 2016
AS4C128M32MD2-18BCN
AS4C128M32MD2-18BIN
Signal Pin Description
Pin
CK, CK
(CK, CK#)
(CK_t, CK_c)
CKE
Type
Input
Function
Clock :
CK and CK are differential clock inputs. All CA inputs are sampled onboth rising and falling
edges of CK. CS and CKE inputs are sampled at the risingedge of CK. AC timings are referenced to
clock.
Clock Enable :
CKE HIGH activates and CKE LOW deactivates the internal clocksignals, input buffers,
and output drivers. Power-saving modes are entered andexited via CKE transitions. CKE is considered
part of the command code. CKE issampled at the rising edge of CK.
Chip Select :
CS is considered part of the command code and is sampled at therising edge of CK.
Input
CS
(CS#)
(CS_n)
CA0~CA9
DM0~DM3
Input
Input
Input
Command/address inputs:
Provide the command and address inputs accordingto the command truth
table.
Input Data Mask :
DM is an input mask signal for write data. Although DM ballsare input-only, the DM
loading is designed to match that of DQ and DQS balls.DM[3:0] is DM for each of the four data bytes,
respectively.
DQ0~DQ31
DQS[3:0]
(DQS_t[3:0]),
DQS[3:0]
DQS#[3:0]
(DQS_c[3:0])
NC
ZQ
VDD1
VDD2
VDDQ
VDDCA
VREFDQ,
VREFCA
VSS
Input/output
Data input/output:
Bidirectional data bus.
Input/output
Data strobe:
The data strobe is bidirectional (used for read and write data) andcomplementary (DQS
and DQS). It is edge-aligned output with read data and centered input with write data. DQS[3:0]/
DQS[3:0] is DQS for each of the four data bytes, respectively.
No Connect:
No internal electrical connection is present.
Input
Supply
Supply
Supply
Supply
Supply
Supply
External impedance (240 ohm):
This signal is used to calibrate the device out-put impedance.
Core power:
Supply 1.
Core power:
Supply 2.
DQ power supply:
Isolated on the die for improved noise immunity.
Command/address power supply:
Command/address power supply.
Reference voltage:
VREFCA is reference for command/address input buffers,VREFDQ is reference
for DQ input buffers.
Common ground
Confidential
-4／103-
Rev.1.0 June 2016
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