DECADE COUNTER;
4-BIT BINARY COUNTER
The SN54 / 74LS290 and SN54 / 74LS293 are high-speed 4-bit ripple type
counters partitioned into two sections. Each counter has a divide-by-two sec-
tion and either a divide-by-five (LS290) or divide-by-eight (LS293) section
which are triggered by a HIGH-to-LOW transition on the clock inputs. Each
section can be used separately or tied together (Q to CP)to form BCD,
Bi-quinary, or Modulo-16 counters. Both of the counters have a 2-input gated
Master Reset (Clear), and the LS290 also has a 2-input gated Master Set
(Preset 9).
SN54/74LS290
SN54/74LS293
DECADE COUNTER;
4-BIT BINARY COUNTER
LOW POWER SCHOTTKY
•
•
•
•
•
Corner Power Pin Versions of the LS90 and LS93
Low Power Consumption . . . Typically 45 mW
High Count Rates . . . Typically 42 MHz
Choice of Counting Modes . . . BCD, Bi-Quinary, Binary
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC
14
MR
13
MR
12
CP1
11
CP0
10
Q0
9
Q3
8
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
J SUFFIX
CERAMIC
CASE 632-08
14
1
14
1
N SUFFIX
PLASTIC
CASE 646-06
LS290
14
1
MS
VCC
14
2
NC
MR
13
3
MS
MR
12
4
Q2
CP1
11
5
Q1
CP0
10
6
NC
Q0
9
7
GND
Q3
8
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LS293
1
NC
2
NC
3
NC
4
Q2
5
Q1
6
NC
7
GND
LOADING
(Note a)
HIGH
LOW
1.5 U.L.
2.0 U.L.
1.0 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
PIN NAMES
Clock (Active LOW going edge) Input to
÷
2 Section.
Clock (Active LOW going edge) Input to
÷
5 Section (LS290).
Clock (Active LOW going edge) Input to
÷
8 Section (LS293).
Master Reset (Clear) Inputs
Master Set (Preset-9, LS290) Inputs
Output from
÷
2 Section (Notes b & c)
Outputs from
÷
5 &
÷
8 Sections (Note b)
CP0
CP1
CP1
MR1, MR2
MS1, MS2
Q0
Q1, Q2, Q3
0.05 U.L.
0.05 U.L.
0.05 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
µA
HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.
c) The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 Input of the device.
FAST AND LS TTL DATA
5-1
SN54/74LS290
D
SN54/74LS293
FUNCTIONAL DESCRIPTION
The LS290 and LS293 are 4-bit ripple type Decade, and
4-Bit Binary counters respectively. Each device consists of
four master / slave flip-flops which are internally connected to
provide a divide-by-two section and a divide-by-five (LS290)
or divide-by-eight (LS293) section. Each section has a
separate clock input which initiates state changes of the
counter on the HIGH-to-LOW clock transition. State changes
of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are
subject to decoding spikes and should not be used for clocks
or strobes. The Q0 output of each device is designed and
specified to drive the rated fan-out plus the CP1 input of the
device.
A gated AND asynchronous Master Reset (MR1
⋅
MR2) is
provided on both counters which overrides the clocks and
resets (clears) all the flip-flops. A gated AND asynchronous
Master Set (MS1
⋅
MS2) is provided on the LS290 which
overrides the clocks and the MR inputs and sets the outputs to
nine (HLLH).
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices
may be operated in various counting modes:
LS290
A. BCD Decade (8421) Counter — the CP1 input must be
LS290 MODE SELECTION
RESET/SET INPUTS
MR1
H
H
X
L
X
L
X
MR2
H
H
X
X
L
X
L
MS1
L
X
H
L
X
X
L
MS2
X
L
H
X
L
L
X
Q0
L
L
H
OUTPUTS
Q1
L
L
L
Q2
Q3
L
L
H
MR1
H
L
H
L
externally connected to the Q0 output. The CP0 input
receives the incoming count and a BCD count sequence is
produced.
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3
output must be externally connected to the CP0 input. The
input count is then applied to the CP1 input and a
divide-by-ten square wave is obtained at output Q0.
C. Divide-By-Two and Divide-By-Five Counter — No external
interconnections are required. The first flip-flop is used as a
binary element for the divide-by-two function (CP0 as the
input and Q0 as the output). The CP1 input is used to obtain
binary divide-by-five operation at the Q3 output.
LS293
A. 4-Bit Ripple Counter — The output Q0 must be externally
connected to input CP1. The input count pulses are applied
to input CP0. Simultaneous division of 2, 4, 8, and 16 are
performed at the Q0, Q1, Q2, and Q3 outputs as shown in
the truth table.
B. 3-Bit Ripple Counter — The input count pulses are applied
to input CP1. Simultaneous frequency divisions of 2, 4, and
8 are available at the Q1, Q2, and Q3 outputs. Independent
use of the first flip-flop is available if the reset function
coincides with reset of the 3-bit ripple-through counter.
LS293 MODE SELECTION
RESET INPUTS
MR2
H
H
L
L
Q0
L
OUTPUTS
Q1
L
Q2
Q3
L
L
L
L
Count
Count
Count
Count
L
Count
Count
Count
TRUTH TABLE
OUTPUT
COUNT
Q0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Q1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
Q2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
Q3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
LS290
BCD COUNT SEQUENCE
COUNT
0
1
2
3
4
5
6
7
8
9
OUTPUT
Q0
L
H
L
H
L
H
L
H
L
H
Q1
L
L
H
H
L
L
H
H
L
L
Q2
L
L
L
L
H
H
H
H
L
L
Q3
L
L
L
L
L
L
L
L
H
H
NOTE: Output Q0 is connected to Input CP1
for BCD count.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Note: Output Q0 connected to input CP1.
FAST AND LS TTL DATA
5-3
SN54/74LS290
•
SN54/74LS293
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Parameter
54
74
54
74
54, 74
54
74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 0.4
4.0
8.0
Unit
V
°C
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
S b l
VIH
VIL
VIK
VOH
Parameter
P
Input HIGH Voltage
54
Input LOW Voltage
74
Input Clamp Diode Voltage
54
Output HIGH Voltage
74
54, 74
VOL
Output LOW Voltage
74
Input HIGH Current
0.1
Input LOW Current
MS, MR
CP0
CP1 (LS290)
CP1 (LS293)
Short Circuit Current (Note 1)
Power Supply Current
–20
–0.4
–2.4
–3.2
–1.6
– 100
15
0.35
0.5
20
IIH
V
µA
mA
2.7
3.5
0.25
0.4
V
V
2.5
– 0.65
3.5
0.8
– 1.5
V
V
Min
2.0
0.7
V
Typ
Max
Unit
U i
V
Test C di i
T
Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
p
g
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
,
,
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
IIL
mA
VCC = MAX, VIN = 0.4 V
IOS
ICC
mA
mA
VCC = MAX
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
5-4
SN54/74LS290
D
SN54/74LS293
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V, CL = 15 pF)
Limits
LS290
Symbol
S b l
fMAX
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
tPHL
tPHL
Parameter
P
CP0 Input Clock Frequency
CP1 Input Clock Frequency
Propagation Delay,
CP0 Input to Q0 Output
CP0 Input to Q3 Output
CP1 Input to Q1 Output
CP1 Input to Q2 Output
CP1 Input to Q3 Output
MS Input to Q0 and Q3 Outputs
MS Input to Q1 and Q2 Outputs
MR Input to Any Output
Min
32
16
10
12
32
34
10
14
21
23
21
23
20
26
26
16
18
48
50
16
21
32
35
32
35
30
40
40
26
40
Typ
Max
Min
32
16
10
12
46
46
10
14
21
23
34
34
16
18
70
70
16
21
32
35
51
51
LS293
Typ
Max
Unit
U i
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
AC SETUP REQUIREMENTS
(TA = 25°C, VCC = 5.0 V)
Limits
LS290
Symbol
S b l
tW
tW
tW
tW
trec
CP0 Pulse Width
CP1 Pulse Width
MS Pulse Width
MR Pulse Width
Recovery Time MR to CP
Parameter
P
Min
15
30
15
15
25
15
25
Max
LS293
Min
15
30
Max
Unit
U i
ns
ns
ns
ns
ns
RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition form HIGH-to-LOW in order to
recognize and transfer HIGH data to the Q outputs.
AC WAVEFORMS
*CP
1.3 V
tW
tPHL
Q
1.3 V
1.3 V
tPLH
1.3 V
Figure 1
*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables.
MR & MS
1.3 V
tW
1.3 V
trec
1.3 V
MS
1.3 V
tW
1.3 V
trec
1.3 V
CP
tPHL
Q
1.3 V
CP
Q0
⋅
Q3
(LS290)
tPLH
1.3 V
Figure 2
Figure 3
FAST AND LS TTL DATA
5-5
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