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SN74LS174
Hex D Flip−Flop
The LSTTL/MSI SN74LS174 is a high speed Hex D Flip-Flop. The
device is used primarily as a 6-bit edge-triggered storage register. The
information on the D inputs is transferred to storage during the LOW
to HIGH clock transition. The device has a Master Reset to
simultaneously clear all flip-flops. The LS174 is fabricated with the
Schottky barrier diode process for high speed and is completely
compatible with all ON Semiconductor TTL families.
http://onsemi.com
•
•
•
•
Edge-Triggered D-Type Inputs
Buffered-Positive Edge-Triggered Clock
Asynchronous Common Reset
Input Clamp Diodes Limit High Speed Termination Effects
16
LOW
POWER
SCHOTTKY
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
I
OH
I
OL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current
−
High
Output Current
−
Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
−0.4
8.0
Unit
V
°C
mA
mA
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
16
1
SOEIAJ
M SUFFIX
CASE 966
ORDERING INFORMATION
Device
SN74LS174N
SN74LS174D
SN74LS174DR2
SN74LS174M
SN74LS174MEL
Package
16 Pin DIP
SOIC−16
SOIC−16
SOEIAJ−16
SOEIAJ−16
Shipping
2000 Units/Box
38 Units/Rail
2500/Tape & Reel
See Note 1
See Note 1
1. For ordering information on the EIAJ version of
the SOIC package, please contact your local
ON Semiconductor representative.
1
Publication Order Number:
SN74LS174/D
©
Semiconductor Components Industries, LLC, 2006
July, 2006
−
Rev. 8
SN74LS174
CONNECTION DIAGRAM DIP
(TOP VIEW)
V
CC
16
Q
5
15
D
5
14
D
4
13
Q
4
12
D
3
11
Q
3
10
CP
9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1
MR
2
Q
0
3
D
0
4
D
1
5
Q
1
6
D
2
7
Q
2
8
GND
LOADING
(Note a)
PIN NAMES
D
0
− D
5
CP
MR
Q
0
− Q
5
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs
HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
mA
HIGH/1.6 mA LOW.
LOGIC SYMBOL
3 4 6 11 13 14
9
1
D
0
D
1
D
2
D
3
D
4
D
5
CP
MR
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
2 5 7 10 12 15
V
CC
= PIN 16
GND = PIN 8
LOGIC DIAGRAM
MR CP D
5
1
9
14
D
4
13
D
3
11
D
2
6
D
1
4
D
0
3
D Q
CP
C
D
15
D Q
CP
C
D
12
D Q
CP
C
D
10
D Q
CP
C
D
7
D Q
CP
C
D
5
D Q
CP
C
D
2
Q
5
Q
4
V
CC
= PIN 16
GND = PIN 8
Q
3
Q
2
Q
1
Q
0
= PIN NUMBERS
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2
SN74LS174
FUNCTIONAL DESCRIPTION
The LS174 consists of six edge-triggered D flip-flops with
individual D inputs and Q outputs. The Clock (CP) and
Master Reset (MR) are common to all flip-flops.
Each D input’s state is transferred to the corresponding
flip-flop’s output following the LOW to HIGH Clock (CP)
transition.
A LOW input to the Master Reset (MR) will force all
outputs LOW independent of Clock or Data inputs. The
LS174 is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
TRUTH TABLE
Inputs (t = n, MR = H)
D
H
L
Note 1: t = n + 1 indicates conditions after next clock.
Outputs (t = n+1) Note 1
Q
H
L
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
V
IH
V
IL
V
IK
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.7
−0.65
3.5
0.25
0.35
0.4
0.5
20
0.1
−0.4
−20
−100
26
Min
2.0
0.8
−1.5
Typ
Max
Unit
V
V
V
V
V
V
μA
mA
mA
mA
mA
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
V
CC
= MIN, I
IN
=
−
18 mA
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
I
OL
= 4.0 mA
I
OL
= 8.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IL
or V
IH
per Truth Table
V
OL
Output LOW Voltage
I
IH
I
IL
I
OS
I
CC
Input HIGH Current
Input LOW Current
Short Circuit Current (Note 2)
Power Supply Current
V
CC
= MAX, V
IN
= 2.7 V
V
CC
= MAX, V
IN
= 7.0 V
V
CC
= MAX, V
IN
= 0.4 V
V
CC
= MAX
V
CC
= MAX
2. Not more than one output should be shorted at a time, nor for more than 1 second.
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3
SN74LS174
AC CHARACTERISTICS
(T
A
= 25°C)
Limits
Symbol
f
MAX
t
PHL
t
PLH
t
PHL
Parameter
Maximum Input Clock Frequency
Propagation Delay, MR to Output
Propagation Delay, Clock to Output
Min
30
Typ
40
23
20
21
35
30
30
Max
Unit
MHz
ns
ns
V
CC
= 5.0 V
C
L
= 15 pF
Test Conditions
AC SETUP REQUIREMENTS
(T
A
= 25°C)
Limits
Symbol
t
W
t
s
t
h
t
rec
Parameter
Clock or MR Pulse Width
Data Setup Time
Data Hold Time
Recovery Time
Min
20
20
5.0
25
Typ
Max
Unit
ns
ns
ns
ns
V
CC
= 5.0 V
Test Conditions
AC WAVEFORMS
1/f
max
t
w
CP
1.3 V
t
s(H)
D
*
1.3 V
t
h(H)
t
s(L)
1.3 V
t
h(L)
1.3 V
t
PHL
1.3 V
CP
Q
t
PHL
1.3 V
1.3 V
MR
1.3 V
t
W
1.3 V
t
rec
1.3 V
1.3 V
t
PLH
1.3 V
Q
*The shaded areas indicate when the input is permitted to
*change
for predictable output performance.
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
DEFINITIONS OF TERMS
SETUP TIME (t
s
) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (t
h
) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (t
rec
) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
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4
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