19-3550; Rev 0; 1/05
Delay Lines for High-Speed Clock
Distribution Systems
General Description
The MAX3620 series is a family of high-performance
passive delay lines for use in QDR/QDRII synchronous
memory systems. These delay lines support high-speed
transceiver logic (HSTL) source terminated transmission
with an unterminated load at the receiver, and deliver
accurate delays of 0.75ns, 1.00ns, 1.25ns, and 1.50ns
for the generation of the quarter clock phase. The
MAX3620 is offered in a small 3mm x 3mm package
which contains two delay lines of equal length that can
be driven either differentially or single-endedly.
♦
All-Passive Design
♦
Compatible with 100Ω Differential and 50Ω Single-
Ended Transmission Lines
♦
Small 3mm x 3mm Package
Features
♦
Supports HSTL Source Terminated Lines
MAX3620
Applications
QDR/QDRII Memory Systems
Multiphase Clock Generation
PART
MAX3620AETT
MAX3620BETT
MAX3620CETT
MAX3620DETT
Ordering Information
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
6 TDFN
6 TDFN
6 TDFN
6 TDFN
Pin Configuration
TOP VIEW
IN1
COMMON
IN2
1
2
3
6
5
4
OUT1
COMMON
OUT2
Selector Guide
PART
MAX3620AETT
MAX3620BETT
MAX3620CETT
MAX3620DETT
PKG CODE
T633-2
T633-2
T633-2
T633-2
TOP MARK
AJX
AIY
AIZ
AJA
MAX3620
*EP
TDFN
*EP—EXPOSED PAD. MUST BE CONNECTED TO THE
SAME POTENTIAL AS COMMON.
Typical Application Circuit
QDR II SRAM CLOCK OUTPUT
HSTL SOURCE TERMINATED
50Ω
IN1
COMMON
DELAY LINE
1/4 CLOCK PERIOD
OUT1
COMMON
50Ω
QDR II SRAM CLOCK INPUT
HSTL HIGH-Z CMOS
90° PHASE
MAX3620
50Ω
IN2
OUT2
50Ω
270° PHASE
50Ω
50Ω
180° PHASE
50Ω
50Ω
0° PHASE
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Delay Lines for High-Speed Clock
Distribution Systems
MAX3620
ABSOLUTE MAXIMUM RATINGS
Maximum DC Voltage between COMMON and IOs
(IN1, IN2, OUT1, OUT2)......................................................±2.0V
Operating Temperature Range ...........................-45°C to +85°C
Storage Temperature Range .............................-55°C to +150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical ambient temperature is +25°C. See Table 1 for more information.)
PARAMETER
Characteristic Impedance
SYMBOL
Z
0
CONDITIONS
See Table 1 clock frequency
MAX3620A
Delay Values
Z
LOAD
= Z
SOURCE
(Note 1)
MAX3620B
MAX3620C
MAX3620D
Delay Matching
IN2-to-OUT2 relative to IN1-to-OUT1,
Z
LOAD
= Z
SOURCE
MAX3620A
Z
LOAD
= Z
SOURCE
(Notes 1, 2, 4)
Insertion Loss
Z
LOAD
>> Z
SOURCE
,
source termination only
(Notes 5, 6)
MAX3620B
MAX3620C
MAX3620D
MAX3620A
MAX3620B
MAX3620C
MAX3620D
MAX3620A
Cutoff Frequency,
3dB Loss Relative to 10MHz
Z
LOAD
= Z
SOURCE
(Note 3)
MAX3620B
MAX3620C
MAX3620D
Input Return Loss
Output Return Loss
Input Leakage at ±1.5V
Output Leakage at ±1.5V
Z
LOAD
= Z
SOURCE
, 50MHz to 1GHz
(Note 3)
Z
LOAD
= Z
SOURCE
, 50MHz to 1GHz
(Note 3)
IN1 or IN2 to grounded COMMON
OUT1 or OUT2 to grounded COMMON
MAX3620A
Z
LOAD
= Z
SOURCE
(Notes 1, 2)
Output Transition Time
(20% to 80%)
Z
LOAD
>> Z
SOURCE
,
source termination only
(Note 5)
MAX3620B
MAX3620C
MAX3620D
MAX3620A
MAX3620B
MAX3620C
MAX3620D
12
15
-10
-10
540
620
700
760
590
720
810
890
ps
+10
+10
0.65
0.90
1.15
1.40
-20
2.5
2.1
2.3
2.2
4.6
3.8
3.1
3.4
450
370
320
300
dB
dB
µA
µA
MHz
dB
MIN
TYP
50
0.75
1.00
1.25
1.50
0.85
1.10
1.35
1.60
+20
ps
ns
MAX
UNITS
Ω
2
_______________________________________________________________________________________
Delay Lines for High-Speed Clock
Distribution Systems
ELECTRICAL CHARACTERISTICS (continued)
(Typical ambient temperature is +25°C. See Table 1 for more information.)
Note 1:
Note 2:
Note 3:
Note 4:
Load and source resistance = 50Ω ±1%, capacitance
≤
1pF. Input transition time (20% to 80%) = 300ps.
The clock frequency is the maximum operational clock frequency listed in Table 1.
Load and source resistance = 50Ω ±1%, capacitance
≤
1pF.
Insertion loss is relative to a lossless 50Ω transmission line. Ideally, an insertion loss of 0dB will result in 0.5 times the open-
circuit transmitter output.
Note 5:
Source termination only (no-load termination), 5pF and 20kΩ at load, 300ps input transition time (20% to 80%). Load capac-
itance dominates performance.
Note 6:
Insertion loss is relative to an ideal open 20kΩ load. Ideally, an insertion loss of 0dB will result in 0.998 times the open-circuit
transmitter output.
MAX3620
Table 1. Recommended Operating Conditions
PARAMETER
Operating Ambient Temperature
Recommended Load Capacitance
Recommended Load Resistance
Z
LOAD
>> 50Ω, source termination only
Z
LOAD
>> 50Ω, source termination only
MAX3620A
Clock Frequency
MAX3620B
MAX3620C
MAX3620D
Input Amplitude
Input Voltage Range
-1.5
250
190
150
125
CONDITIONS
MIN
-40
TYP
+25
5
20
333
250
200
167
1.5
+1.5
V
P-P
V
MHz
MAX
+85
UNITS
°C
pF
kΩ
_______________________________________________________________________________________
3
Delay Lines for High-Speed Clock
Distribution Systems
MAX3620
Typical Operating Characteristics
(T
A
= +25°C, unless otherwise noted.)
DELAY vs. R
LOAD
(LOW LOAD RESISTANCE)
MAX3620 toc01
DELAY vs. R
LOAD
(HIGH LOAD RESISTANCE)
MAX3620 toc02
DELAY vs. C
LOAD
(LOW LOAD RESISTANCE)
R
LOAD
= 50Ω
MAX3620D
MAX3620C
MAX3620 toc03
1.75
C
LOAD
= 1.0pF
1.50
DELAY (ns)
MAX3620D
1.75
C
LOAD
= 5.0pF
1.50
MAX3620D
1.75
1.50
DELAY (ns)
DELAY (ns)
1.25
MAX3620C
1.00
MAX3620B
0.75
1.25
MAX3620C
1.25
MAX3620B
1.00
MAX3620B
0.75
1.00
0.75
MAX3620A
MAX3620A
MAX3620A
0.50
30
40
50
R
LOAD
(Ω)
60
70
0.50
0.50
15 16 17 18 19 20 21 22 23 24 25
R
LOAD
(kΩ)
0
2
4
6
8
10
C
LOAD
(pF)
DELAY vs. C
LOAD
(HIGH LOAD RESISTANCE)
R
LOAD
= 20Ω
MAX3620D
1.50
DELAY (ns)
MAX3620 toc04
MAX3620A S11
MAX3620 toc05
MAX3620B S11
-3
-6
-9
-12
dB
-15
-18
-21
-24
MAX3620 toc06
1.75
0
-3
-6
-9
0
1.25
dB
MAX3620C
-12
-15
-18
1.00
MAX3620B
0.75
MAX3620A
0.50
0
2
4
6
8
10
C
LOAD
(pF)
-21
-24
-27
-30
10
100
FREQUENCY (MHz)
1000
50MHz
-27
-30
10
50MHz
100
FREQUENCY (MHz)
1000
MAX3620C S11
MAX3620 toc07
MAX3620D S11
MAX3620 toc08
MAX3620A S22
-3
-6
-9
-12
dB
-15
-18
-21
-24
MAX3620 toc09
0
-3
-6
-9
-12
dB
-15
-18
-21
-24
-27
-30
10
100
FREQUENCY (MHz)
50MHz
0
-3
-6
-9
-12
dB
-15
-18
-21
-24
-27
-30
50MHz
10
100
FREQUENCY (MHz)
0
-27
-30
1000
10
50MHz
100
FREQUENCY (MHz)
1000
1000
4
_______________________________________________________________________________________
Delay Lines for High-Speed Clock
Distribution Systems
Typical Operating Characteristics (continued)
(T
A
= +25°C, unless otherwise noted.)
MAX3620
MAX3620B S22
MAX3620 toc10
MAX3620C S22
MAX3620 toc11
MAX3620D S22
-3
-6
-9
-12
dB
-15
-18
-21
-24
MAX3620 toc12
0
-3
-6
-9
-12
dB
-15
-18
-21
-24
-27
-30
10
100
FREQUENCY (MHz)
50MHz
0
-3
-6
-9
-12
dB
-15
-18
-21
-24
-27
-30
50MHz
10
100
FREQUENCY (MHz)
0
-27
-30
1000
10
50MHz
100
FREQUENCY (MHz)
1000
1000
Pin Description
PIN
1
2
3
4
5
6
—
NAME
IN1
COMMON
IN2
OUT2
COMMON
OUT1
Exposed
Pad
Common
Single-Ended Input 2
Single-Ended Output 2
Common
Single-Ended Output 1
Connect to same potential as COMMON
IN2
OUT2
FUNCTION
Single-Ended Input 1
IN1
OUT1
COMMON
COMMON
Figure 1. Functional Diagram
Detailed Description
The MAX3620 delay lines are transmission lines con-
structed with a series of L-C sections.
Figure 1 is a
functional diagram of the MAX3620. The distributed
architecture of the MAX3620 allows for symmetrical
impedance looking into each terminal. When the
MAX3620 is used in single-ended operation, leave
unused input/output open.
_______________________________________________________________________________________
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
