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89HPES4T4ZBBCGI: 产品描述PCI Interface IC PCI EXPRESS SWITCH; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小334KB，共30页; 制造商IDT (Integrated Device Technology); 标准

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89HPES4T4ZBBCGI概述

PCI Interface IC PCI EXPRESS SWITCH

89HPES4T4ZBBCGI规格参数

参数名称	属性值
Brand Name	Integrated Device Technology
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	IDT (Integrated Device Technology)
零件包装代码	CABGA
包装说明	CABGA-144
针数	144
制造商包装代码	BCG144
Reach Compliance Code	compliant
ECCN代码	EAR99
Samacsys Confidence	3
Samacsys Status	Released
Samacsys PartID	11322056
Samacsys Pin Count	144
Samacsys Part Category	Integrated Circuit
Samacsys Package Category	BGA
Samacsys Footprint Name	144-LEAD BGA [13 X 13]
Samacsys Released Date	2020-01-24 12:25:47
Is Samacsys	N
地址总线宽度
总线兼容性	PCI
最大时钟频率	125 MHz
外部数据总线宽度
JESD-30 代码	S-PBGA-B144
JESD-609代码	e1
长度	13 mm
湿度敏感等级	3
端子数量	144
最高工作温度	85 °C
最低工作温度	-40 °C
封装主体材料	PLASTIC/EPOXY
封装代码	LBGA
封装等效代码	BGA144,12X12,40
封装形状	SQUARE
封装形式	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）	260
电源	1,3.3 V
认证状态	Not Qualified
座面最大高度	1.5 mm
最大供电电压	1.1 V
最小供电电压	0.9 V
标称供电电压	1 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	30
宽度	13 mm
uPs/uCs/外围集成电路类型	BUS CONTROLLER, PCI
Base Number Matches	1

文档解析

89HPES4T4是IDT公司PRECISE™家族中的一款PCI Express（PCIe）开关解决方案。这款4通道、4端口的外围芯片执行PCI Express基础层（Base）交换功能。它提供连接和交换功能，能够在一个PCI Express上游端口和多达四个下游端口之间进行数据传输，并支持下游端口之间的交换。

以下是89HPES4T4芯片PCI Express开关架构的一些关键特点和工作原理：

高性能PCI Express开关：芯片拥有四个2.5 Gbps的PCI Express通道，支持x1上游端口和三个x1下游端口。它采用低延迟直通（cut-through）开关架构，支持最大有效载荷（payload）大小达到256字节。
灵活的架构与配置选项：芯片支持所有端口的自动车道反转（lane reversal）和自动极性反转（polarity inversion），能够从串行EEPROM加载设备配置。
集成度高的解决方案：不需要外部组件，芯片内部集成了用于数据包缓冲和排队的内存，并且集成了四个2.5 Gbps嵌入式SerDes（Serializer/Deserializer），带有8B/10B编码器/解码器，无需单独的收发器。
可靠性、可用性和可服务性（RAS）特性：内部端到端奇偶校验保护所有TLP（传输层数据包），确保数据完整性，即使在不实现端到端CRC（ECRC）的系统中也是如此。支持ECRC和高级错误报告，兼容PCI Express原生热插拔、热交换I/O。
电源管理：采用先进的低功耗设计技术，实现低典型功耗。支持PCI电源管理接口规范（PCIPM 1.2），未使用的SerDes会被禁用。支持高级配置和电源接口规范（ACPI）2.0，支持活动链接状态。
可测试性和调试特性：内置伪随机比特流（PRBS）发生器，多个SerDes测试模式，能够绕过链路训练并强制任何链路进入任何模式，提供统计和性能计数器。
通用输入/输出（GPIO）引脚：提供5个GPIO引脚，每个引脚可以单独配置为输入或输出，也可以配置为中断输入，每个引脚具有可选择的备用功能。
热插拔接口：支持每个下游端口的PCI Express热插拔。通过SMBus主接口与外部I/O扩展器连接，以减少设备上所需的引脚数量。
系统时钟参数：芯片的系统时钟参数包括输入参考时钟频率范围、输入时钟占空比、输入时钟上升/下降时间、输入时钟抖动等。
电气特性：包括PCI Express接口的差分输入电压摆动、接收器差分输入电压（峰-峰值）、差分输入阻抗等。

89HPES4T4芯片通过这些特性和工作原理，实现了高效的数据传输和灵活的系统配置，适用于需要x1连接、低延迟和简化板级布局的应用程序。

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4-Lane 4-Port

PCI Express® Switch

89HPES4T4

Data Sheet

The 89HPES4T4 is a member of IDT’s PRECISE™ family of PCI

Express switching solutions. The PES4T4 is a 4-lane, 4-port peripheral

chip that performs PCI Express Base switching. It provides connectivity

and switching functions between a PCI Express upstream port and up to

four downstream ports and supports switching between downstream

ports.

Device Overview



Features



High Performance PCI Express Switch

– Four 2.5 Gbps PCI Express lanes

– Four switch ports

– x1 Upstream port

– Three x1 Downstream ports

– Low latency cut-through switch architecture

– Support for Max payload sizes up to 256 bytes

– One virtual channel

– Eight traffic classes

– PCI Express Base Specification Revision 1.1 compliant

Flexible Architecture with Numerous Configuration Options

– Automatic lane reversal on all ports

– Automatic polarity inversion on all lanes

– Ability to load device configuration from serial EEPROM

Legacy Support

– PCI compatible INTx emulation

– Bus locking



Highly Integrated Solution

– Requires no external components

– Incorporates on-chip internal memory for packet buffering and

queueing

– Integrates four 2.5 Gbps embedded SerDes with 8B/10B

encoder/decoder (no separate transceivers needed)

Reliability, Availability, and Serviceability (RAS) Features

– Internal end-to-end parity protection on all TLPs ensures data

integrity even in systems that do not implement end-to-end

CRC (ECRC)

– Supports ECRC and Advanced Error Reporting

– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O

– Compatible with Hot-Plug I/O expanders used on PC mother-

boards

Power Management

– Utilizes advanced low-power design techniques to achieve low

typical power consumption

– Supports PCI Power Management Interface specification (PCI-

PM 1.2)

– Unused SerDes are disabled.

– Supports Advanced Configuration and Power Interface Speci-

fication, Revision 2.0 (ACPI) supporting active link state

Testability and Debug Features

– Built in Pseudo-Random Bit Stream (PRBS) generator

– Numerous SerDes test modes

– Ability to bypass link training and force any link into any mode

– Provides statistics and performance counters

Block Diagram

4-Port Switch Core / 4 PCI Express Lanes

Frame Buffer

Route Table

Port

Arbitration

Scheduler

Transaction Layer

Data Link Layer

Transaction Layer

Data Link Layer

Transaction Layer

Data Link Layer

Transaction Layer

Data Link Layer

Mux / Demux

Phy

Logical

Layer

Mux / Demux

Phy

Logical

Layer

Mux / Demux

Phy

Logical

Layer

Mux / Demux

Phy

Logical

Layer

SerDes

(Port 0)

(Port 2)

(Port 3)

(Port 4)

Figure 1 Internal Block Diagram

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

1 of 30



2014 Integrated Device Technology, Inc.

June 12, 2014

IDT 89HPES4T4 Data Sheet



5 General Purpose Input/Output Pins

– Each pin may be individually configured as an input or output

– Each pin may be individually configured as an interrupt input

– Each pin has a selectable alternate function

Option A Package: 13mm x 13mm 144-ball BGA with 1mm ball spacing

Option B Package: 10mm x 10mm 132-ball QFN with 1mm ball spacing

Product Description

Utilizing standard PCI Express interconnect, the PES4T4 provides the most efficient fan-out solution for applications requiring x1 connectivity, low

latency, and simple board layout with a minimum number of board layers. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully

compliant with PCI Express Base specification 1.1.

The PES4T4 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transac-

tion layers in compliance with PCI Express Base specification Revision 1.1. The PES4T4 can operate either as a store and forward or cut-through

switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated

resource management to allow efficient switching for applications requiring additional narrow port connectivity and also some high-end connectivity.

Processor

North

Bridge

Memory

South

Bridge

PES4T4

LOM

1394

Figure 2 I/O Expansion Application

SMBus Interface

The PES4T4 contains an SMBus master interface. This master interface allows the default configuration register values of the PES4T4 to be over-

ridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O

expander. Two pins make up the SMBus master interface. These pins consist of an SMBus clock pin and an SMBus data pin.

Hot-Plug Interface

The PES4T4 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES4T4 utilizes

an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, when-

ever the state of a Hot-Plug output needs to be modified, the PES4T4 generates an SMBus transaction to the I/O expander with the new value of all of

the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate

function of GPIO) of the PES4T4. In response to an I/O expander interrupt, the PES4T4 generates an SMBus transaction to read the state of all of the

Hot-Plug inputs from the I/O expander.

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June 12, 2014

89HPES4T4ZBBCGI相似产品对比

	89HPES4T4ZBBCGI	89HPES4T4ZBBCG8	89HPES4T4ZBBCI8
描述	PCI Interface IC PCI EXPRESS SWITCH	PCI Interface IC PCI EXPRESS SWITCH	PCI Interface IC PCI EXPRESS SWITCH
Brand Name	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology
是否无铅	不含铅	不含铅	含铅
是否Rohs认证	符合	符合	不符合
零件包装代码	CABGA	CABGA	CABGA
包装说明	CABGA-144	LBGA, BGA144,12X12,40	CABGA-144
针数	144	144	144
制造商包装代码	BCG144	BCG144	BC144
Reach Compliance Code	compliant	compliant	not_compliant
ECCN代码	EAR99	EAR99	EAR99
总线兼容性	PCI	PCI; SMBUS	PCI; SMBUS
JESD-30 代码	S-PBGA-B144	S-PBGA-B144	S-PBGA-B144
JESD-609代码	e1	e1	e0
长度	13 mm	13 mm	13 mm
湿度敏感等级	3	3	3
端子数量	144	144	144
最高工作温度	85 °C	70 °C	85 °C
最低工作温度	-40 °C	-	-40 °C
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LBGA	LBGA	LBGA
封装等效代码	BGA144,12X12,40	BGA144,12X12,40	BGA144,12X12,40
封装形状	SQUARE	SQUARE	SQUARE
封装形式	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）	260	260	225
电源	1,3.3 V	1,3.3 V	1,3.3 V
认证状态	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.5 mm	1.5 mm	1.5 mm
最大供电电压	1.1 V	1.1 V	1.1 V
最小供电电压	0.9 V	0.9 V	0.9 V
标称供电电压	1 V	1 V	1 V
表面贴装	YES	YES	YES
技术	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	COMMERCIAL	INDUSTRIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Lead (Sn63Pb37)
端子形式	BALL	BALL	BALL
端子节距	1 mm	1 mm	1 mm
端子位置	BOTTOM	BOTTOM	BOTTOM
处于峰值回流温度下的最长时间	30	NOT SPECIFIED	NOT SPECIFIED
宽度	13 mm	13 mm	13 mm
uPs/uCs/外围集成电路类型	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI
Base Number Matches	1	1	1
厂商名称	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	-

89HPES4T4ZBBCGI

89HPES4T4ZBBCGI在线购买

89HPES4T4ZBBCGI概述

89HPES4T4ZBBCGI规格参数

文档解析

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89HPES4T4ZBBCGI相似产品对比

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