Features
•
Low-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
•
•
•
•
– 2.7 (V
CC
= 2.7V to 5.5V)
– 1.8 (V
CC
= 1.8V to 3.6V)
Internally Organized 65,536 x 8
Two-wire Serial Interface
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility
Write Protect Pin for Hardware and Software Data Protection
128-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Max)
High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years
Automotive Devices Available
8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP,
8-lead LAP, 8-lead SAP and 8-ball dBGA2 Packages
Die Sales: Wafer Form, Waffle Pack and Bumped Die
Two-wire Serial
EEPROM
512K (65,536 x 8)
AT24C512
Note: Not recommended for new
design; please refer to
AT24C512B datasheet.
Description
The AT24C512 provides 524,288 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s
cascadable feature allows up to four devices to share a common two-wire bus. The
device is optimized for use in many industrial and commercial applications where low-
power and low-voltage operation are essential. The devices are available in space-
saving 8-pin PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead
Leadless Array (LAP), and 8-lead SAP packages. In addition, the entire family is avail-
able in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.
Table 1.
Pin Configurations
Pin Name
A0–A1
SDA
SCL
WP
NC
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
No Connect
A0
A1
NC
GND
8-lead TSSOP
A0
A1
NC
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
NC
GND
8-lead PDIP
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8-lead SOIC
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8-ball dBGA2
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
8-lead Leadless Array
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
A0
A1
NC
GND
VCC
WP
SCL
SDA
8-lead SAP
8
7
6
5
1
2
3
4
A0
A1
NC
GND
A0
A1
NC
GND
Bottom View
Bottom View
Bottom View
Rev. 1116O–SEEPR–1/07
1
Absolute Maximum Ratings*
Operating Temperature..................................–55°C to +125°C
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................... –1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Figure 1.
Block Diagram
2
AT24C512
1116O–SEEPR–1/07
AT24C512
Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/ADDRESSES (A1, A0):
The A1 and A0 pins are device address inputs that are
hardwired or left not connected for hardware compatibility with other AT24Cxx devices.
When the pins are hardwired, as many as four 512K devices may be addressed on a
single bus system (device addressing is discussed in detail under the
Device Address-
ing section.
If the pins are left floating, the A1 and A0 pins will be internally pulled down
to GND if the capacitive coupling to the circuit board V
CC
plane is <3 pF. If coupling is
>3 pF, Atmel recommends connecting the address pins to GND.
WRITE PROTECT (WP):
The write protect input, when connected to GND, allows nor-
mal write operations. When WP is connected high to V
CC
, all write operations to the
memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down
to GND if the capacitive coupling to the circuit board V
CC
plane is <3 pF. If coupling is
>3 pF, Atmel recommends connecting the pin to GND. Switching WP to V
CC
prior to a
write operation creates a software write protect function.
Memory Organization
AT24C512, 512K SERIAL EEPROM:
The 512K is internally organized as 512 pages of
128-bytes each. Random word addressing requires a 16-bit data word address.
3
1116O–SEEPR–1/07
Table 2.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +1.8V
Symbol
C
I/O
C
IN
Note:
Test Condition
Input/Output Capacitance (SDA)
Input Capacitance (A
0
, A
1
, SCL)
1. This parameter is characterized and is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Table 3.
DC Characteristics
Applicable over recommended operating range from: T
AI
=
–
40°C to +85°C, V
CC
= +1.8V to +5.5V, T
AC
= 0°C to +70°C,
V
CC
= +1.8V to +5.5V (unless otherwise noted)
Symbol
V
CC1
V
CC2
V
CC3
I
CC1
I
CC2
I
SB1
I
SB2
I
SB3
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Note:
Parameter
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current
Supply Current
Standby Current
(1.8V option)
Standby Current
(2.7V option)
Standby Current
(5.0V option)
Input Leakage Current
Output Leakage
Current
Input Low Level
(1)
Input High Level
(1)
Output Low Level
Output Low Level
V
CC
= 3.0V
V
CC
= 1.8V
I
OL
= 2.1 mA
I
OL
= 0.15 mA
V
CC
= 5.0V
V
CC
= 5.0V
V
CC
= 1.8V
V
CC
= 3.6V
V
CC
= 2.7V
V
CC
= 5.5V
V
CC
= 4.5 - 5.5V
V
IN
= V
CC
or V
SS
V
OUT
= V
CC
or V
SS
–0.6
V
CC
x 0.7
READ at 400 kHz
WRITE at 400 kHz
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
0.10
0.05
Test Condition
Min
1.8
2.7
4.5
1.0
2.0
Typ
Max
3.6
5.5
5.5
2.0
3.0
1.0
3.0
2.0
6.0
6.0
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
µA
µA
µA
V
V
V
V
µA
Units
V
V
V
mA
mA
µA
1. V
IL
min and V
IH
max are reference only and are not tested.
4
AT24C512
1116O–SEEPR–1/07
AT24C512
Table 4.
AC Characteristics
Applicable over recommended operating range from T
A
=
–
40°C to +85°C, V
CC
= +1.8V to +5.5V, C
L
= 100 pF (unless oth-
erwise noted) Test conditions are listed in Note 2.
1.8 Volt
Symbol
f
SCL
t
LOW
t
HIGH
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
(1)
Notes:
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
Time the bus must be free before a
new transmission can start
(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time
(1)
Inputs Fall Time
(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C, Page Mode
100K
4.7
100
20
or
5
(3)
100K
4.7
4.0
0.1
4.7
4.0
4.7
0
200
1.0
300
0.6
50
10
or
5
(3)
100K
4.5
Min
Max
100
1.3
1.0
0.05
1.3
0.6
0.6
0
100
0.3
300
0.25
50
10
or
5
(3)
0.9
Min
2.7 Volt
Max
400
0.4
0.4
0.05
0.5
0.25
0.25
0
100
0.3
100
0.55
Min
5.0 Volt
Max
1000
Units
kHz
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
Write Cycles
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
R
L
(connects to V
CC
): 1.3 kΩ (2.7V, 5V), 10 kΩ (1.8V)
Input pulse voltages: 0.3V
CC
to 0.7V
CC
Input rise and fall times:
≤50
ns
Input and output timing reference voltages: 0.5V
CC
3. The Write Cycle Time of 5 ms only applies to the AT24C512 devices bearing the process letter “A” on the package (the mark
is located in the lower right corner on the top side of the package).
5
1116O–SEEPR–1/07
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