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NLV74VHC04DTR2G

产品描述Logic Gates LOG CMOS INVERTER HEX
产品类别逻辑    逻辑   
文件大小78KB,共5页
制造商ON Semiconductor(安森美)
官网地址http://www.onsemi.cn
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NLV74VHC04DTR2G概述

Logic Gates LOG CMOS INVERTER HEX

NLV74VHC04DTR2G规格参数

参数名称属性值
Brand NameON Semiconductor
是否无铅不含铅
厂商名称ON Semiconductor(安森美)
包装说明TSSOP,
制造商包装代码948G-01
Reach Compliance Codecompliant
Factory Lead Time4 weeks
系列AHC/VHC/H/U/V
JESD-30 代码R-PDSO-G14
JESD-609代码e4
长度5 mm
逻辑集成电路类型INVERTER
湿度敏感等级1
功能数量6
输入次数1
端子数量14
最高工作温度85 °C
最低工作温度-40 °C
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度)NOT SPECIFIED
传播延迟(tpd)12 ns
座面最大高度1.2 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)2 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式GULL WING
端子节距0.65 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度4.4 mm

文档预览

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MC74VHC04
Hex Inverter
The MC74VHC04 is an advanced high speed CMOS inverter
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems
to 3 V systems.
Features
http://onsemi.com
MARKING DIAGRAMS
14
High Speed: t
PD
= 3.8 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
= 2
mA
(Max) at T
A
= 25°C
High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2 V to 5.5 V Operating Range
Low Noise: V
OLP
= 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 36 FETs or 9 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
1
2
1
SOIC−14
D SUFFIX
CASE 751A
1
14
TSSOP−14
DT SUFFIX
CASE 948G
1
1
A
WL, L
Y
WW, W
G or
G
VHC04G
AWLYWW
VHC
04
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
A1
Y1
A1
V
CC
A6
Y6
A5
Y5
A4
Y4
14
1
FUNCTION TABLE
Inputs
A
L
H
Outputs
Y
H
L
A2
3
4
Y2
Y1
A2
13
2
3
12
A3
5
6
Y3
Y=A
Y2
A3
Y3
Y5
GND
8
7
11
4
A4
9
8
Y4
10
5
6
ORDERING INFORMATION
Device
MC74VHC04DR2G
Package
SOIC−14
(Pb−Free)
Shipping
2500 / Tape &
Reel
2500 / Tape &
Reel
9
A5
11
10
A6
13
12
Y6
MC74VHC04DTR2G TSSOP−14
(Pb−Free)
Figure 1. Logic Diagram
Figure 2. Pinout:
14−Lead Packages
(Top View)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2014
1
September, 2014 − Rev. 6
Publication Order Number:
MC74VHC04/D

 
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