NJW1503A
PLL Synthesizer with 3-Wire Bus for TV Tuner
DESCRIPTION
The NJW1503A is a PLL frequency synthesizer especially designed
for TV and VCR tuning systems and consists of PLL circuit and a
prescaler which operates up to 1.0GHz, built into one chip.
The NJW1503A is controlled through a 3-wire bus.
FEATURES
•
Operating Voltage 5V
•
Low Operating Current : 15mA typ. @Vcc=5V
•
Prescaler accepts frequencies up to 1GHz on chip
•
3-wire bus controlled
•
Reference divider ratio automatic setting (512 or 1024)
•
34V max. tuning voltage output
•
Package Outline: SSOP16
PACKAGE OUTLINE
NJW1503AV
BLOCK DIAGRAM
VCC1
5V GND
BS0-BS3
VCC3
BAND SW
4bit
4bit
Latch
3Wire Bus
Receiver
CS
DAT
CLK
HF IN
PreAMP
CP
VCC2
1/8
Programmable
Divider 15bit
15bit
Latch
8bit
Latch
OSCOUT
Phase
OUT
AMP
Phase
Comp
1/1024
1/512
(1/640)
Ref
Divider
X’tal
OSC
XTAL
AMPOUT
-1-
NJW1503A
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Supply Voltage (Vcc1,3)
Vcc1,Vcc3
Supply Voltage (Vcc2)
Vcc2
Input Voltage(except 3-wire bus)
Vi
Output Voltage
Vo
(except 3-wire bus)
3-Wire bus Input Voltage
V
seri
Power Dissipation
Operating Temperature Range
Storage Temperature Range
P
D
T
opr
T
stg
(T
A
=25°C)
Ratings
Unit
-0.3 to +6.5
V
-0.3 to +34
V
-0.3 to Vcc+0.3
V
-0.3 to Vcc+0.3
-0.3 to 6.5
300
-20 to +75
-40 to +125
V
V
mW
°C
°C
(T
A
=25°C)
Max.
Unit
5.5
V
34
V
4.05
MHz
1000
MHz
-
uS
-
uS
-
uS
-
uS
-
uS
100
KHz
RECOMMENDED OPERATING CONDITION
Parameter
Condition
Symbol
Operating Voltage
Vcc1,Vcc3
V
+1
,V
+3
Operating Voltage
Vcc2
V
+2
X’tal Operating Range
f
xtal
HF Input Frequency
Input= -20dBm
f
hf
Data Set-up Time
t
SET
Clock Width Time
t
CLK
Refer to 3-Wire bus Timing Chart
Data Hold Time
t
HOLD
CS Set-up Time
t
CSSET
CS Hold Time
t
CSHLD
Maximum Clock
Refer to 3-Wire bus Timing Chart
t
CLKMAX
Frequency
F
CLKMAX
=1/T
CLKMAX
Min.
4.5
0
3.15
80
2
2
2
10
2
-
Typ.
5
32
4
-
-
-
-
-
-
-
DAT
CLK
T
SET
T
CLK
T
HOLD
T
CLKMAX
CS
T
CSSET
T
CSHOLD
3-Wire bus Timing Chart
V
IH
min(0.7 Vcc1) and V
IH
max(0.3 Vcc1)
-2-
NJW1503A
ELECTRICAL CHARACTERISTICS
Parameter
Condition
Operating Current 1
f
HF
=100MHz
Operating Current 2
AMPOUT: Low Level
AMP Input Current
Phase OUT :High Imp (2.5V)
ANP OUT : Low Level
AMP Output Current
AMP OUT Input=5V
AMP Gain
f=1KHz
Phase Comparator
Current Source
Current
Phase Comparator
Current Sink
Current
Band Switch
“L” Output Current
BS0=BS1=BS2=0.3V
“H” Output Current
BS0=BS1=BS2=4.7V
“L” Output Current
BS=0.3V
“H” Output Current
BS3=4.7V
3-Wire bus
“H” Input Current
CLK, DAT, CS Terminal
“L” Input Current
CLK, DAT, CS Terminal
“H” Input Voltage Range
CLK, DAT, CS Terminal
“L” Input Voltage Range
CLK, DAT, CS Terminal
(Vcc1,3=5V,Vcc2=32V,T
A
=25°C)
Symbol Min.
Typ. Max.
Unit
I
CC
6
15
23
mA
I
CC
2
-
1.6
-
mA
I
IN
(-50)
0.1
(50)
nA
I
OUT
AV
I
sourse
I
sink
I
OBS0-2L
I
OBS0-2H
I
OBS3L
I
OBS3H
I
IN
H
I
IN
L
V
IH
V
IL
-
40
190
-400
-5.0
11.0
-6.0
0.7
-5
-5
4.0
0
-
50
280
-280
-0.5
15.0
-1.0
3.5
0
0
-
-
-2.5
60
400
-190
0.0
-
-0.4
-
5
5
5.0
1.0
mA
dB
uA
uA
mA
mA
mA
mA
uA
uA
V
V
-3-
NJW1503A
TEST CIRCUIT
VS3
5V
2mV
1kHz
VS2
2.5V
CS
DAT
CLK
34V
270
18p
100
4MHz
100
100
316k
16
XTAL
15
CS
14
DAT
13
CLK
12
OSC OUT
11
VCC2
10
AMP OUT
9
CP
BS0
VCC1
GND
VCC3
BS3
BS2
1
1n
2
3
4
5
6
BS1
HF
7
8
50
SG
-20dBm
5V
COUNTER
VS1
4.7V or 0.3V
-4-
NJW1503A
Serial Bus Data Format (3-Wire bus)
1. Bus protocol for18bit
B3 B2 B1 B0 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0
Reference divider : f
xtal
1/512
2. Bus protocol for19bit
B3 B2 B1 B0 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0
Reference divider : f
xtal
1/1024
3. Bus protocol for Test (27bit)
B3 B2 B1 B0 N14 N13 ...N1 N0 T7 T6 T5 T4 T3 T2 T1 T0
B0 to B3
: Control of Band Switch
N14=MSB N0=LSB
Division ratio
: N=2
14
×N14+2
13
× N13+······+2
1
×N1+N0
256
N0 to N14 : Control of Programmable Divider
Maximum division ratio 32767
Minimum division ratio
T0 to T7
: Control bit of test
Bit T0: Charge Pump Current
T0
Charge Pump Current
0
280uA
1
60uA
Bit T1 and T2: Output function of Phase Comparator
T2
T1
Phase Comparator
0
0
Normal Operation
0
1
Source
1
High Impedance
1
0
Sink
1
Bit T4: Band Switch Test
T4
Band Switch
0
Normal Operation
1
Test
Bit T5 and T6: Reference Divider
T6
T5
Reference Divider
0
0
1/512
0
1
1/1024
*
1/640
1
* : don’t care; 0 or 1
Conditions
Normal, Default
Test
Conditions
Normal, Default
Test
Test
Test
Conditions
Normal, Default
Test
Condition
Normal, Default
The 18bit and 19bit is automatic selector of the reference divider.
T3: unassigned, undefined
(Note)
Default : Power on reset
-5-
嵌入式系统
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