Changes to Ordering Guide .......................................................... 15
Rev. D | Page 2 of 15
Data Sheet
SPECIFICATIONS
DUAL SUPPLY
AD7228
V
DD
= 10.8 V to 16.5 V, V
SS
= −5 V ± 10%, GND = 0 V, V
REF
= 2 V to 10 V, R
L
= 2 kΩ, C
L
= 100 pF, unless otherwise noted. All
specifications T
MIN
to T
MAX
, −40°C to +85°C unless otherwise noted. V
OUT
must be less than V
DD
by 3.5 V to ensure correct operation.
Table 1.
Parameter
STATIC PERFORMANCE
Resolution
Total Unadjusted Error (TUE)
1
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
2
Zero Code Error
at 25°C
T
MIN
to T
MAX
Minimum Load Resistance
REFERENCE INPUT
Voltage Range
Input Resistance
Input Capacitance
3
AC Feedthrough
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Leakage Current
Input Capacitance
3
Input Coding
DYNAMIC PERFORMANCE
3
Voltage Output Slew Rate
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
Digital Crosstalk
4
POWER SUPPLIES
V
DD
Range
V
SS
Range
I
DD
at 25°C
T
MIN
to T
MAX
I
SS
at 25°C
T
MIN
to T
MAX
1
2
K and B
Versions
8
±2
±1
±1
±1
L and C
Versions
8
±1
±1/2
±1
±1/2
Unit
Bits
LSB max
LSB max
LSB max
LSB max
Test Conditions/Comments
V
DD
= 15 V ± 10%, V
REF
= 10 V
Guaranteed monotonic
Typical temperature coefficient is 5 ppm/°C with
V
REF
= 10 V
Typical temperature coefficient is 30 µV/°C
V
OUT
= 10 V
±25
±30
2
2/10
2
500
−70
2.4
0.8
±1
8
Binary
2
5
5
50
50
10.8/16.5
−4.5/−5.5
16
20
14
18
±15
±20
2
2/10
2
500
−70
2.4
0.8
±1
8
Binary
2
5
5
50
50
10.8/16.5
−4.5/−5.5
16
20
14
18
mV max
mV max
kΩ min
V min/V max
kΩ min
pF max
dB typ
V min
V max
µA max
pF max
Occurs when each DAC is loaded with all 1s
V
REF
= 8 V p-p sine wave at 10 kHz
V
IN
= 0 V or V
DD
V/µs min
µs max
µs max
nV-sec typ
nV-sec typ
V min/V max
V min/V max
mA max
mA max
Outputs unloaded; V
IN
= V
INL
or V
INH
mA max
mA max
V
REF
= 10 V; settling time to ±1/2 LSB
V
REF
= 10 V; settling time to ±1/2 LSB
Code transition all 0s to all 1s, V
REF
= 0 V; WR = V
DD
Code transition all 0s to all 1s, V
REF
= 10 V; WR = 0 V
For specified performance
For specified performance
Outputs unloaded; V
IN
= V
INL
or V
INH
Total unadjusted error includes zero code error, relative accuracy, and full-scale error.
Calculated after zero code error is adjusted out.
3
Sample tested at T
A
= 25°C to ensure compliance.
4
The glitch impulse transferred to the output of one converter (not addressed) due to a change in the digital input code to another addressed converter.
Rev. D | Page 3 of 15
AD7228
SINGLE SUPPLY
Data Sheet
V
DD
= 15 V ± 10%, V
SS
= GND, GND = 0 V, V
REF
= 10 V, R
L
= 2 kΩ, C
L
= 100 pF, unless otherwise noted. All specifications T
MIN
to T
MAX
,
−40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE
Resolution
Total Unadjusted Error
1
Differential Nonlinearity
Minimum Load Resistance
REFERENCE INPUT
Input Resistance
Input Capacitance
2
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Leakage Current
Input Capacitance
2
Input Coding
DYNAMIC PERFORMANCE
2
Voltage Output Slew Rate
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
Digital Crosstalk
3
POWER SUPPLIES
V
DD
Range
I
DD
at 25°C
T
MIN
to T
MAX
1
2
K and B
Versions
8
±2
±1
2
2
500
2.4
0.8
±1
8
Binary
2
5
7
50
50
13.5/16.5
16
20
L and C
Versions
8
±1
±1
2
2
500
2.4
0.8
±1
8
Binary
2
5
7
50
50
13.5/16.5
16
20
Unit
Bits
LSB max
LSB max
kΩ min
kΩ min
pF max
V min
V max
µA max
pF max
Test Conditions/Comments
Guaranteed monotonic
V
OUT
= 10 V
Occurs when each DAC is loaded with all 1s
V
IN
= 0 V or V
DD
V/µs min
µs max
µs max
nV-sec typ
nV-sec typ
V min/V max
mA max
mA max
Settling time to ±1/2 LSB
Settling time to ±1/2 LSB
Code transition all 0s to all 1s, V
REF
= 0 V, WR = V
DD
Code transition all 0s to all 1s, V
REF
= 10 V, WR = 0 V
For specified performance
Outputs unloaded; V
IN
= V
INL
or V
INH
Total unadjusted error includes zero code error, relative accuracy and full-scale error.
Sample tested at T
A
= 25°C to ensure compliance.
3
The glitch impulse transferred to the output of one converter (not addressed) due to a change in the digital input code to another addressed converter.
Rev. D | Page 4 of 15
Data Sheet
SWITCHING CHARACTERISTICS
AD7228
See Figure 8 and Figure 2; V
DD
= 5 V ± 5% or 10.8 V to 16.5 V; V
SS
= 0 V or –5 V ± 10%. Sample tested at 25°C to ensure compliance. All
input rise and fall times measured from 10% to 90% of 5 V, t
R
= t
F
= 5 ns. Timing measurement reference level is (V
INH
+ V
INL
)/2.
Table 3.
Parameter
t
1
t
2
t
3
t
4
t
5
Limit at 25°C,
All Grades
0
0
70
10
95
Limit at T
MIN
, T
MAX
,
K, L, B, and C Versions
0
0
90
10
120
t
1
ADDRESS
Unit
ns min
ns min
ns min
ns min
ns min
t
2
Description
Address to WR setup time
Address to WR hold time
Data valid to WR setup time
Data valid to WR hold time
Write pulse width
5V
0V
5V
0V
t
5
WR
t
3
DATA
V
INH
V
INL
t
4
5V
0V
NOTES
1. THE SELECTED INPUT LATCH IS TRANSPARENT WHILE WR
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