HIGH-SPEED
8K x 8 DUAL-PORT
STATIC RAM
Features
◆
◆
IDT7005S/L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 20/35/55ns (max.)
– Commercial:15/17/20/25/35/55ns (max.)
Low-power operation
– IDT7005S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7005L
Active: 700mW (typ.)
Standby: 1mW (typ.)
IDT7005 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Devices are capable of withstanding greater than 2001V
electrostatic discharge
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PGA, PLCC and a 64-pin thin quad
flatpack
Industrial temperature range (-40°C to +85°C) is available for
selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
A
12L
A
0L
(1,2)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
Address
Decoder
13
(1,2)
MEMORY
ARRAY
13
Address
Decoder
A
12R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
M/S
SEM
R
INT
R
(2)
2738 drw 01
MARCH 2018
1
©2018 Integrated Device Technology, Inc.
DSC 2738/19
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM. The
IDT7005 is designed to be used as a stand-alone 64K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-
more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM
approach in 16-bit or wider memory system applications results in full-
speed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 750mW of power. Low-power (L) versions
offer battery backup data retention capability with typical power consump-
tion of 500µW from a 2V battery.
The IDT7005 is packaged in a ceramic 68-pin PGA, 68-pin PLCC
and a 64-pin thin quad flatpack, (TQFP). Military grade product is
manufactured in compliance with MIL-PRF-38535 QML making it ideally
suited to military temperature applications demanding the highest level of
performance and reliability.
Pin Configurations
(1,2,3)
I/O
6R
I/O
5R
I/O
4R
I/O
3R
V
CC
I/O
2R
I/O
1R
I/O
0R
GND
V
CC
I/O
7L
I/O
6L
GND
I/O
5L
I/O
4L
I/O
3L
I/O
2L
26
I/O
7R
N/C
OE
R
R/W
R
SEM
R
CE
R
N/C
N/C
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
7005J
J68
(4)
2
1
68
67
66
65
64
63
62
61
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
I/O
1L
I/O
0L
N/C
OE
L
R/W
L
SEM
L
CE
L
N/C
N/C
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
2738 drw 02
A
4R
A
3R
A
2R
A
1R
A
0R
INT
R
BUSY
R
M/S
GND
BUSY
L
INT
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
M/S
BUSY
R
BUSY
L
INT
R
GND
A
0L
INT
L
A
0R
A
1R
A
2R
A
3R
A
4L
A
3L
A
2L
A
5L
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
V
CC
N/C
CE
L
SEM
L
R/W
L
OE
L
I/O
0L
I/O
1L
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32
49
50
31
51
30
52
29
28
53
54
55
56
57
58
59
60
61
62
63
64
1 2
3
4
5 6
7 8
27
26
25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
A
1L
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
GND
N/C
CE
R
SEM
R
R/W
R
OE
R
I/O
7R
I/O
6R
7005
PN64
(4)
6.42
2
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
GND
I/O
6L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
7L
V
CC
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J68 package body is approximately .95 in x .95 in x .12 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
2738 drw 03
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
11
53
A
7L
55
A
9L
51
50
A
5L
A
4L
52
A
6L
54
A
8L
49
A
3L
48
A
2L
47
A
1L
46
44
42
A
0L
BUSY
L
M/S
40
38
INT
R
A
1R
36
A
3R
35
A
4R
32
A
7R
30
A
9R
34
A
5R
33
A
6R
31
A
8R
10
45
43
41
39
37
INT
L
GND
BUSY
R
A
0R
A
2R
09
08
57
56
A
11L
A
10L
59
58
V
CC
A
12L
61
N/C
60
N/C
07
29
28
A
11R
A
10R
7005G
G68
(4,5)
26
GND
24
N/C
27
A
12R
25
N/C
06
05
63
62
SEM
L
CE
L
65
64
OE
L
R/W
L
67
66
I/O
0L
N/C
04
23
22
SEM
R
CE
R
20
OE
R
21
R/W
R
03
02
1
3
5
7
9
18
19
68
11
13
15
I/O
1L
I/O
2L
I/O
4L
GND I/O
7L
GND I/O
1R
V
CC
I/O
4R
I/O
7R
N/C
2
4
I/O
3L
I/O
5L
A
B
C
6
8
I/O
6L
V
CC
D
E
10
12
14
16
17
I/O
0R
I/O
2R
I/O
3R
I/O
5R
I/O
6R
F
G
H
J
K
L
2738 drw 04
01
INDEX
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.18in x 1.18in x .16in.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking
Pin Names
Left Port
CE
L
R/W
L
OE
L
A
0L
- A
12L
I/O
0L
- I/O
7L
SEM
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A
0R
- A
12R
I/O
0R
- I/O
7R
SEM
R
INT
R
BUSY
R
M/S
V
CC
GND
Right Port
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2738 tbl 01
Names
6.42
3
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
Outputs
CE
H
L
L
X
R/W
X
L
H
X
OE
X
X
L
H
SEM
H
H
H
X
I/O
0-7
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected: Power-Down
Write to Memory
Read Memory
Outputs Disabled
Mode
NOTE:
1. A
0L
– A
12L
is not equal to A
0R
– A
12R
2738 tbl 02
Truth Table II: Semaphore Read/Write Control
(1)
Inputs
(1)
Outputs
CE
H
H
L
R/W
H
↑
X
OE
L
X
X
SEM
L
L
L
I/O
0-7
DATA
OUT
DATA
IN
____
Mode
Read in Semaphore Flag Data Out
Write I/Oo into Semaphore Flag
Not Allowed
2738 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from I/O
0 -
I/O
7.
These eight semaphores are addressed by A
0
- A
2.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect to
GND
Temperature Under
Bias
Storage
Temperature
DC Output Current
Commercial
& Industrial
-0.5 to +7.0
Military
-0.5 to +7.0
Unit
V
Maximum Operating Temperature
and Supply Voltage
(1,2)
Grade
Military
Ambient
Temperature
-55
O
C to+125
O
C
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
OV
Vcc
5.0V
+
10%
5.0V
+
10%
5.0V
+
10%
2738 tbl 05
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
-65 to +135
-65 to +150
50
o
C
C
Commercial
Industrial
o
mA
2738 tbl 04
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
2 Industrial temperature: for specific speeds, packages and powers contact
your sales office.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 10% for more than 25% of the cycle time or 10% maximum,
and is limited to < 20mA for the period of V
TERM
> Vcc + 10%.
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
2738 tbl 06
Capacitance
(1)
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
2738 tbl 07
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
NOTES:
1. These parameters are determined by device characterization but are not production tested
(TQFP Package only).
2. 3dV references the interpolated capacitance when the input and output signals switch from
0V to 3V or from 3V to 0V.
6.42
4
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the 0perating
Temperature and Supply Voltage Range
(V
CC
= 5.0V ± 10%)
7005S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
Min.
___
___
___
7005L
Max.
10
10
0.4
___
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
2738 tbl 08
2.4
2.4
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
Data Retention Characteristics Over All Temperature Ranges
(L Version Only)
(V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
Symbol
V
DR
I
CCDR
Parameter
V
CC
for Data Retention
Data Retention Current
V
CC
= 2V
CE
> V
HC
V
IN
> V
HC
or < V
LC
t
CDR
(3)
t
R
(3)
Chip Deselect to Data Retention Time
Operation Recovery Time
SEM
> V
HC
Mil. & Ind.
Com'l.
Test Condition
Min.
2.0
___
___
Typ.
(1)
___
Max.
___
Unit
V
µA
100
100
___
___
4000
1500
___
___
0
t
RC
(2)
ns
ns
2738 tbl 09
NOTES:
1. T
A
= +25°C, V
CC
= 2V, and are not production tested.
2. t
RC
= Read Cycle Time
3. This parameter is guaranteed by characterization, but is not production tested.
Data Retention Waveform
DATA RETENTION MODE
V
CC
4.5V
t
CDR
V
DR
CE
V
IH
V
IH
2738 drw 05
V
DR
> 2V
4.5V
t
R
6.42
5
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